1597 Tcl Jobs - Page 21

Job ID 2025-14545 Date posted Jul. 12, 2025 Location Bengaluru, India Category Design Engineering Job Description: As part of the methodology team, the Hardware Frontend Flow Developer will be responsible for designing, developing, and deploying scalable and automated flows to support frontend hardware engineering activities. This role demands strong programming skills, experience with hardware toolchains, and a passion for automation and process improvement. The engineer will play a key role in integrating tools, handling sophisticated workflows, and supporting SoC and IP integration efforts. Responsibilities: Develop and deploy robust and reusable flows using C++ and Python for frontend hardware processes. Integrate third-party and internal EDA tools into end-to-end automation frameworks. Build and manage filelists, BOMs, and configuration assets for IP and SoC integration. Streamline and automate repetitive tasks to improve efficiency across teams. Implement and maintain scripts and build systems using Makefile, CMake, Bash, and TCL. Support job scheduling and workflow management using LSF. Collaborate with multi-functional teams to align flows with evolving frontend design needs. Required Skills and Experience: 3-6 years of experience in C++ and Python for flow and tool development. Solid understanding of scripting languages such as TCL, Perl, and Bash. Hands-on experience building and deploying complex hardware engineering flows. Solid understanding of IP and SoC integration concepts. Experience handling filelists and Bill of Materials (BOMs). Confirmed ability to integrate EDA tools into cohesive workflows. Passion for automation and driving efficiency. Familiarity with Makefile, CMake, and workflow schedulers like LSF. Proficiency in shell scripting (bash/tcsh). “Nice To Have” Skills and Experience: Experience with version control systems like Git. Understanding of CI/CD concepts and tools. Working knowledge of HDLs like VHDL or Verilog. Familiarity with Electronic Design Automation (EDA) tools and flows. In Return: We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding! Partner and dedication towards or customers Collaborate and communication Originality and resourcefulness Team and personal development Impact and influence Deliver on your promises Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arm’s hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. #LI-SA3 Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Description Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply! About The Role Ampere Computing is looking for a qualified design engineer on power analysis, optimization, and validation, to contribute in designing our high-performance power-efficient microprocessor chipset. This person will be a part of the Silicon Engineering team and work across multiple groups to drive the power requirements, and power optimization from micro-architecture to final silicon. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Power analysis engineer is expected have strong CMOS design fundamentals and deep knowledge of power reduction techniques at various levels of abstraction. Expertise in analyzing the results given by various power estimation tools and create actionable items for power reduction. Experience in developing flows and post processing scripts to help in analysis and rollup. What You’ll Achieve Setup power analysis environment for at the RTL-level, and gate-level for power analysis of all design blocks at the pre-silicon stage. Determine tests and benchmarks to run on all blocks for pre-silicon power analysis Develop tests in DV test environment to certain use cases interesting for power analysis and reduction Run and review power analysis reports at the RTL-level and gate-level on all design blocks. Identify areas of improvements at the architecture-level, RTL-level, and synthesis. Analyze power from activities from workloads run on emulation environment Determine power optimization budgets for all blocks, and setup runs to validate them as the design progresses. Understand the different CPU use cases, Memory and Pcie workloads. Work with industry standard power analysis tools like Spyglass/Power Artist/Joules/PrimePower etc. Maintain and improve existing power modeling and analysis flows. About You Experience with power analysis using gate-level and RTL-power analysis tools Good understanding of power analysis and optimization on CMOS designs Good understanding of clock-gating, power-gating, DVFS, etc. used for power optimization Good understanding of processor designs, processor work-loads. Solid programming and scripting skills using Perl/Python/Tcl Experience running power analysis on activity from emulation environment Owned CPU or SOC design blocks and familiar with design flows (synthesis, place & route, power, timing, EM/IR) Owned power analysis methodology and/or automation in previous role Hands-on working experience with Power analysis tools and flows (one or more of the following industry-standard tools: Primepower, PTPX, Power Artist, Joules, Voltus) Advanced knowledge of Python, TCL and shell scripting M.Tech in Electronics Engineering or Computer Engineering with 6+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 8+ years of semiconductor experience What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER The Role The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors in a fast-paced environment with cutting-edge technology. The Person Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. Key Responsibilities Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk Preferred Experience 12+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc. Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. Academic Credentials Qualification: Bachelors or Masters in Electronics/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job Title: Memory Design Engineer Experience Required: 2+ Years Location: Bangalore Job Type: Full-time Industry: Semiconductors / VLSI / Memory IP Job Summary: We are seeking a skilled Memory Design Engineer to join our advanced memory IP development team. The candidate will be responsible for architecting, designing, and validating high-performance and low-power memory blocks (e.g., SRAM, ROM, Register Files) for use in SoCs and ASICs across leading-edge process technologies. Key Responsibilities: Design custom memory circuits such as SRAM, ROM, CAM, Register Files, or eFuse. Work closely with layout, verification, and technology teams to ensure optimal performance, power, and area (PPA). Perform transistor-level circuit design, simulation, and optimization for speed, power, and robustness. Analyze and simulate key circuits: sense amplifiers, bitline pre-charge, wordline drivers, decoders, write drivers, etc. Run simulations across PVT corners using tools like HSPICE, Spectre, or XA. Collaborate with layout teams for floorplanning and to ensure DRC/LVS clean layouts. Perform post-layout simulations and analysis (IR drop, EM, aging). Participate in memory characterization, yield improvement, and silicon bring-up support. Contribute to memory compiler development (if applicable). Required Skills and Experience: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical Engineering, or VLSI. 2+ years of experience in full custom memory design. Strong background in analog/mixed-signal CMOS circuit design. Proficiency in simulation tools: HSPICE, Spectre, FastSPICE, XA. Experience with design in advanced nodes (e.g., 28nm, 16nm, 7nm, 5nm, FinFET). Familiarity with ESD, IR drop, EM, and reliability analysis techniques. Understanding of process variation and Monte Carlo simulations. Good debugging, problem-solving, and documentation skills. Preferred Qualifications: Experience with memory compiler architecture/design. Knowledge of radiation-hardened memory (RHBD) or safety-compliant memory (ISO 26262). Scripting knowledge (e.g., Python, Perl, Tcl) for automation. Exposure to silicon bring-up and correlation to simulation results.

Hi All, Lead RTL Design Engineers Experience Level:10+ years of RTL design and development Job Description: Silicon Design Engineer Location: Hyderabad and Bangalore Basic Job Deliverable: Silicon Design Engineer (RTL Design and Development) o Responsible for RTL design and development o Responsible for generating documents, such as requirements specification, design, user-guide, Interface specification, etc., o Experience:  Experience in documenting, designing, implementing complex designs Experience in designing HW/SW interfaces  Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools  Experience with RTL design of Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA technologies  Experience in HW testing, including working with test equipment – logic and traffic analysers, test generators, etc.  Excellent ability to analyze and isolate RTL and test bench issues, RTL and SW issues  Experience in understanding of software and designing HW interfaces for software  Strong debugging skills at device and board level  Scripting language experience like Perl, Python or TCL  Excellent interpersonal, written and verbal communication skills  Excellent communication, problem solving and analytical skills Qualification:B.Tech/M.Tech (CSE/ECE/EEE) - Track record of high academic achievement Regards, K Himabindu Mail ID: himabindu.jeevarathnam@acldigital.com

Hi All, ACL Digital is hiring #Senior #Design #Verification Engineer! Experience: 4 Years Location: Bangalore / Hyderabad Notice Period: Immediate to 30 Days Preferred! We're seeking experienced professionals ASIC/SoC verification. If you have expertise in UVM/System Verilog, proficiency in scripting languages like Python/Perl/TCL, and a strong grasp of protocols such as AXI, APB, PCIe, and DDR. Thanks, K Himabindu

Qualcomm India Private Limited is looking for a skilled and dedicated EM/IR Methodology Engineer to join their team. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering experience. - OR Master's degree in relevant field with 2+ years of experience. - OR PhD in relevant field with 1+ year of experience. Key Responsibilities: - Develop and optimize methodologies for Electromigration (EM) and Voltage Drop (IR) analysis. - Collaborate with design, CAD, and physical implementation teams to optimize power delivery networks. - Enhance workflows for improved PDN analysis efficiency. - Partner with EDA tool vendors to enhance EM/IR analysis tools. - Support design teams in EM/IR verification and sign-off. Required Skills and Qualifications: - Bachelors or Masters degree in Electronics, Electrical Engineering, or related field. - 3-7 years of experience in EM/IR analysis or physical design methodology. - Strong understanding of EM and IR concepts. - Hands-on experience with EM/IR analysis tools such as Voltus, RedHawk, Totem, or equivalent. - Experience with advanced technologies like 2.5D/3D-IC, CoWoS, InFO, and WoW. - Exposure to AI/ML concepts will be a bonus. - Proficiency in scripting languages like Python, Perl, or Tcl. - Good understanding of STA concepts. - Strong problem-solving and analytical skills. - Excellent communication and teamwork skills. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. The company expects its employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes on behalf of individuals. If you are interested in this role, please contact Qualcomm Careers for more information.,

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Job Description Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076998

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X). Senior/Lead PD Engineer ADI is looking for Senior/Lead PD Engineer for the development of complex mixed Signal SoCs. These chips are manufactured in most leading edge process nodes and high speed clock rates. These SoCs involve multiple processor cores and speed signal processing hardware running at high speed. Position Requirements BTech/MTech degree in Electrical/Electronic from a reputed institute with 4-8 years of experience in the field of Digital place and route Hands on experience with the implementation (PnR Signoff) of complex high speed SoC designs in cutting edge process technologies (22 nm, 16 nm, 7 nm, etc). Hands on experience in handling the tapeout of complex high speed SoC designs in cutting edge process technologies Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction Strong expertise in Static Timing analysis , constraint development and sign off. Innovate on the flows to meet the QoR targets and ensure predictability Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage. Being proficient in TCL, Perl etc. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days

Job Description As part of the methodology team, the Hardware Frontend Flow Developer will be responsible for designing, developing, and deploying scalable and automated flows to support frontend hardware engineering activities. This role demands strong programming skills, experience with hardware toolchains, and a passion for automation and process improvement. The engineer will play a key role in integrating tools, handling sophisticated workflows, and supporting SoC and IP integration efforts. Responsibilities Develop and deploy robust and reusable flows using C++ and Python for frontend hardware processes. Integrate third-party and internal EDA tools into end-to-end automation frameworks. Build and manage filelists, BOMs, and configuration assets for IP and SoC integration. Streamline and automate repetitive tasks to improve efficiency across teams. Implement and maintain scripts and build systems using Makefile, CMake, Bash, and TCL. Support job scheduling and workflow management using LSF. Collaborate with multi-functional teams to align flows with evolving frontend design needs. Required Skills and Experience 3-6 years of experience in C++ and Python for flow and tool development. Solid understanding of scripting languages such as TCL, Perl, and Bash. Hands-on experience building and deploying complex hardware engineering flows. Solid understanding of IP and SoC integration concepts. Experience handling filelists and Bill of Materials (BOMs). Confirmed ability to integrate EDA tools into cohesive workflows. Passion for automation and driving efficiency. Familiarity with Makefile, CMake, and workflow schedulers like LSF. Proficiency in shell scripting (bash/tcsh). “Nice To Have” Skills and Experience Experience with version control systems like Git. Understanding of CI/CD concepts and tools. Working knowledge of HDLs like VHDL or Verilog. Familiarity with Electronic Design Automation (EDA) tools and flows. In Return We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding! Partner and dedication towards or customers Collaborate and communication Originality and resourcefulness Team and personal development Impact and influence Deliver on your promises Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arm’s hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What You'll do: Implementation with emphasis on Physical Verification & project finishing/tapeout activities Own and execute Physical Verification flow with in-depth experience in analysing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues ( Calibre/ICV ) Own and execute PV activities at the block and sub-system levels Work closely with PD team in addressing PV issues and provide solutions Contribute to SoC-level PV sign-off checks What You'll Need: 10+ years of Physical verification experience Experience with physical verification checks - DRC, LVS, Antenna, ERC, PERC, ESD etc. using Calibre/ICV Excellent debugging skills and experience with fixing base DRC, metal DRC, especially w.r.t. double/triple patterning layers in advanced process nodes Hands-on experience in DRC/LVS fixing in Innovus/Fusion Compiler environment is a must Good hands-on LVS/antenna debug/fixes along with exposure to runtime reduction techniques Good understanding and hands-on scripting skills in Unix, Perl, Python, SVRF and Tcl to enable high-quality and on-time tapeouts Good understanding of full chip integration and flows is a plus ' ' We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

DESCRIPTION Amazon Lab126 is an inventive research and development company that designs and engineers high-profile devices like the Kindle family of products. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc. Since then, we have worked to produce best-selling e-readers and tablets, as well as new inventions like Echo line of products, Fire TV and Fire phone. What will you help us create? Key job responsibilities As a Senior Electrical Validation Engineer, you will be part of Validation team that is exploring new hardware designs to improve our devices. In this role, you will create, define and develop electrical validation environment and test suites. You will also be responsible for the development of methodologies, execution of validation plans, debug of failures and follow up to closure. Key job responsibilities You will work closely with multi-disciplinary groups including Board Design, System Architects, IP developers, and Software Engineering, to verify and deliver complex, high volume SoCs that enable development of world-class hardware devices. In this role, you will: Perform electrical compliance test specifications / compliance test suite for various interfaces and conduct lab measurements Work on high-speed serial I/O interfaces like (LP)DDR4/5, USB, CSI/DSI, HDMI, PCIe interfaces etc. Perform documentation and communicate data across large number of tests and measurement results Drive initiatives to improve process, procedures, and quality of High Speed Characterization at SOC & Product level. Work on schematic and PCB physical design tools to interpret the design and locate physical probe points. BASIC QUALIFICATIONS Bachelor’s degree or higher in EE, ECE, or CS with atleast 10+ years of Industry experience High speed serial interface analog building blocks, protocol, specifications and test methods Proficiency in handling High Bandwidth oscilloscopes, BERT, logic analyzers and understanding of probing techniques Understanding of Power & signal integrity concepts such as differential impedance, jitter, insertion loss, return loss, termination, etc. PCB layout best practices Good understanding of High-Speed Analog/Digital Circuits, VLSI, semiconductor physics PREFERRED QUALIFICATIONS MS/ME in Computer Science, Electrical Engineering, or related field Writing Python/TCL/PERL code to automate test procedures Good software architecture principles and development practices Scripting experience in any programming language (C++, Python, PERL, MATLAB) to develop automation scripts is a plus. Experience in Analog IP Characterization (SerDes, PLL, DDR) is desirable. Familiarity with Transmitter and Receiver design blocks. Understanding of equalization techniques (CTLE/DFE). Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Job details IND, KA, Bengaluru Devices Hardware & eero Hardware Development

Category Engineering Hire Type Employee Job ID 10344 Remote Eligible No Date Posted 14/04/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. You thrive in a collaborative environment and are excited to work closely with global teams on the latest technology nodes. You have a strong understanding of semiconductor device physics and digital design, and you possess a solid foundation in CMOS fundamentals. Your familiarity with Unix/Shell/Python/TCL is an added advantage, and you are eager to leverage these skills to contribute to innovative projects. Your attention to detail and problem-solving abilities make you an ideal candidate for this role. What You’ll Be Doing: Designing and developing physical IP such as SERDES, DDR, and/or Memory as part of the Logic Libraries team. Collaborating with global teams to implement and optimize layout designs on the latest technology nodes. Utilizing your understanding of CMOS fundamentals to ensure high-quality and efficient design processes. Employing Unix/Shell/Python/TCL scripting to automate and enhance design workflows. Conducting design reviews and providing feedback to improve overall design quality and performance. Staying updated with the latest industry trends and technological advancements to ensure cutting-edge designs. The Impact You Will Have: Contributing to the development of high-performance silicon chips that power a wide range of applications. Enhancing the efficiency and reliability of physical IP design processes. Supporting the advancement of semiconductor technology through innovative layout designs. Collaborating with global teams to achieve project milestones and deliver high-quality designs. Improving the overall performance and functionality of Synopsys' technology solutions. Driving the continuous technological innovation that shapes the future of the industry. What You’ll Need: Strong understanding of semiconductor device physics and digital design principles. Solid foundation in CMOS fundamentals. Experience with Unix/Shell scripting and familiarity with Python/TCL. Proficiency in layout design and development of physical IP. Ability to work collaboratively with global teams and communicate effectively. Who You Are: Detail-oriented with strong analytical and problem-solving skills. Innovative and eager to stay updated with industry trends and advancements. Collaborative team player with excellent communication skills. Proactive and able to manage multiple tasks effectively. Passionate about semiconductor technology and its applications. The Team You’ll Be A Part Of: You will be part of the Logic Libraries team, a group of dedicated professionals focused on designing and developing high-performance physical IP. This team collaborates with global counterparts to implement the latest technology nodes and deliver cutting-edge solutions. Together, you will drive the innovation that powers the future of semiconductor technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Join Our Aprisa Team! Aprisa is looking for Siemens EDA ambassadors. Siemens EDA is a global technology leader in Electronic Design Automation software. Their software tools empower companies worldwide to develop innovative electronic products efficiently. By using these tools, customers are able to advance technology and physics boundaries to deliver superior products in the complex realm of chip, board, and system design. This is your role. Aprisa provides comprehensive functionality for top-level hierarchical design and block-level implementation for intricate digital IC designs. The detail-route-centric architecture and hierarchical database at Aprisa facilitate the acceleration of design closure and attainment of optimal quality results within a driven runtime. Aprisa is currently engaged in developing the next-generation RTL-to-GDSII solution and is seeking individuals to join this pioneering journey. **Role:** - Drive and oversee the design and development of various aspects of RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. - Guide and lead team members towards successful project completion by introducing innovative and effective solutions. - Collaborate with a dedicated team of experts. **Must-Have Requirements:** - Bachelor's or Master's degree in CSE/EE/ECE from a reputable engineering college with 8-12 years of experience in software development. - Proficient in C/C++, algorithms, and data structures. - Strong problem-solving and analytical skills. - Leadership abilities to inspire and support the team with your expertise. **Great to Have Experience in:** In this role, you will have the opportunity to work with RTL synthesis tools and engage with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Furthermore, you will be involved in designing C or RTL IPs, optimizing RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly appreciated, along with your proficiency in scripting languages like Python and TCL. Join Siemens, a diverse collective of over 377,000 individuals shaping the future in more than 200 countries. Siemens is committed to equality and encourages applications that reflect the diversity of the communities where they operate. Employment decisions at Siemens are based on qualifications, merit, and business requirements. Embrace your curiosity and creativity to help shape tomorrow!,

Quest Global is a leading organization known for its innovation and rapid growth in the engineering services sector. With a rich domain expertise and a strong presence in the top OEMs across seven industries, we are a company with a 25-year legacy and a vision to reach a centennial milestone. Driven by ambition, passion, and humility, we are on a journey to shape the future through engineering. We are in search of individuals who embody the spirit of humble geniuses, believing in the power of engineering to turn the impossible into reality. Our ideal candidates are innovators inspired by technology and driven to design, develop, and test solutions as trusted partners for Fortune 500 clients. As a diverse team of engineers, we understand that our work goes beyond technical solutions; we are shaping a brighter future for all. If you are eager to contribute to meaningful projects and be part of an organization that values collective success and learning from failures, we invite you to join us. We are looking for achievers and courageous challenge-crushers who possess the following skills and characteristics: Responsibilities: - Performing floor-planning and routing studies at block and full-chip level - Executing top-level floorplan and clock pushdown to Partition - IO Planning and bump planning - Collaboration with Package team to meet Die file milestones - Conducting full chip and partition level timing analysis - Exploring low power techniques and power reduction opportunities - Designing and analyzing clock distribution - Executing Physical verification activities at full-chip level - Leading technical activities of physical design throughout technology readiness, design, and execution Qualifications: - Proficiency in Netlist2GDSII Implementation, including Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, and Chip finishing - Experience in Physical Design Methodologies and sub-micron technology of 16nm and lower nodes - Handling designs with >1M instance count and 1 GHz frequency - Programming skills in Tcl/Tk/Perl for automating design processes and enhancing efficiency - Hands-on experience with PNR Suite from Cadence & Synopsys (Innovus & ICC2) - Strong background in Static Timing Analysis (PrimeTime SI), EM/IR-Drop analysis (PT-PX, Redhawk), and Physical Verification (Calibre) Education Type: M.E/M.Tech/MS-VLSI Design & Embedded System Job Type: Full Time-Regular Experience Level: Mid Level Total Years of Experience: 5 - 8,

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. Perform design optimizations for area, power, and performance. Conduct design reviews and ensure compliance with coding standards and best practices. Work closely with verification teams to develop test plans and ensure 100% functional coverage. Debug and resolve design and integration issues during simulation and post-silicon validation. Participate in timing analysis and closure in collaboration with the physical design team. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2-10 years of experience in RTL design and implementation for VLSI systems. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. Experience in static timing analysis (STA) and timing closure workflows. Strong problem-solving skills and the ability to debug complex design issues. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: Experience with low-power design and multi-clock domain systems. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. Familiarity with machine learning or AI-based RTL optimizations. Why Join Us Work on groundbreaking projects in VLSI design and technology. Collaborate with a team of industry experts in a supportive and innovative environment. Opportunities for career growth and continuous learning. Competitive salary and benefits. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!,

Join Our Aprisa Team! Aprisa is looking for Siemens EDA ambassadors who are passionate about electronic design automation software. As a global technology leader, Siemens EDA provides innovative tools that empower companies worldwide to develop cutting-edge electronic products efficiently. By utilizing our software solutions, our customers can navigate the complexities of chip, board, and system design while pushing the boundaries of technology and physics to deliver superior products. Your Role: As part of the Aprisa team, you will play a crucial role in the development of top-level hierarchical design and block-level implementation for complex digital IC designs. Leveraging our detail-route-centric architecture and hierarchical database, you will expedite design closure and achieve optimal quality results within a driven runtime. Join us in shaping the next-generation RTL-to-GDSII solution and become an integral part of this innovative journey! Key Responsibilities: - Drive and oversee the design and development of various components of RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. - Provide guidance and leadership to ensure successful project completion through innovative and effective solutions. - Collaborate with a dedicated team of experts to achieve common goals. Requirements: - Hold a B.Tech or M.Tech degree in CSE/EE/ECE from a reputable engineering college with 8-12 years of experience in software development. - Possess a strong grasp of C/C++, algorithms, and data structures. - Demonstrate exceptional problem-solving and analytical skills. - Lead and motivate the team with your expertise. Desirable Experience: You will have the opportunity to: - Develop RTL synthesis tools and engage with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. - Design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. - Utilize parallel algorithms and job distribution strategies, along with proficiency in scripting languages like Python and TCL. Join Siemens: Siemens is a global community of over 377,000 individuals working together to shape the future across 200 countries. We value diversity and equality, and we welcome applications that represent the various communities we serve. Employment decisions at Siemens are based on qualifications, merit, and business requirements. Embrace your curiosity and creativity to help us pioneer tomorrow!,

Meet the Team Internet became a reality because of Cisco and its intelligent innovations in WAN engineering over multiple decades. We are reinventing WAN now and disrupting the market. If you love the challenge of building a highly scalable intelligent distributed system, then please join the party. We are abstracting WAN infrastructure and programmatically building a highly flexible controller-based software defined solution to provide intent based networking. Our solutions provide secure connectivity to user & device from anywhere in the world to their favorite application running in cloud, on premise or as SaaS. We give the opportunity to learn and innovate in a vast technology space of Routing, Security, Analytics, Telemetry, Distributed System, Machine learning and endless other areas. We strive to create an open and transparent culture where we embrace new ideas with open arms. Hardware Routing Platform Software under Catalyst Engineering Routing team builds industry leading Headend SDWAN and Edge routing platforms (Catalyst 8500, Catalyst 8000 and ASR1000) is part of a bigger team that is currently working on building next generation routing and services in controller-based network deployment at scale, enabling the customers to avail secure, reliable, and fast connectivity in a highly distributed SDWAN fabric spanning across the globe connecting thousands of devices and millions of users. Join us and be part of the high energy team, help transform and build intelligent internet. Your Impact You will have the opportunity to work with leading-edge networking technologies in the areas of SDWAN and edge routing platforms and be part of the team responsible for defining, developing, and innovating new and evolving features and architectures in SDWAN and routing. You will work in collaboration with team who will define the next generation ASIC for routing products which would require new architecture for packet forwarding. You will participate in many creative projects, with the authority and scope to apply your expertise in a dynamic engineering environment. Our team values collaboration, learning, paramount focus on quality and customer impact. You will get a chance to work with various teams across varied technologies and will learn and be part of an ever growing, evolving technology. You will be responsible for crafting, coding and testing forwarding components with focus on end-to-end visibility and knowledge. You will have the opportunity to influence the network behavior by collaborating with other Engineers, Technical Leaders and Distinguished engineers across multiple cross-functional teams in Cisco. This role is for you if you believe you are passionate about problem solving, can articulate problems in a way that people start seeing solutions in it as well. You are someone who challenges the status quo and a driver of change. Minimum Qualifications and Requirement: * 10-14 years of Industry experience. Hands on experience on End-to-End Software development in a networking company in areas of Platforms, Hardware, bring up, system software, drivers (kernel and user space), bootloaders, BIOS and performance engineering/tuning * Strong C programming in Linux and device drivers with skills and familiarity with large software development projects in an UNIX or IOS environment including experience with source code control systems, i.e. ability to search, navigate and handle extremely large code base. * Experience with LAN/WAN communication interfaces, Ethernet layer 2, layer 3 technologies. * Experience with hardware and software debuggers, GDB, Arium, BDI. * Experience with scripting and automation and to be able to design, create and run scripts for longevity tests for platform, e.g Shell, Python, Perl, TCL, Expect. The successful candidate will participate on project teams defining and developing innovative new products based on Cisco technology. Key functions are following: * Develop, enhance, verify and sustain embedded system software for complex internetworking products as a key member of a cross-functional team. * Perform design trade-off analysis, write software specifications, code, integrate and test new software and hardware, complete product release, and provide field support. * Interface with Business Development, External Partners, Hardware Engineering, QA Test and Release Operations throughout the development cycle. *Act as Key Decision maker on Technical and Engineering Design issues. Desirable skills: * Knowledge or demonstrated experience with high-speed interfaces, PHY, MAC, MACSEC experience will be a plus. * Some of the key areas of expertise in addition to Networking domain is platform/System Areas such as kernel bring up, kernel driver development, platform bring up/ management software and Cloud Networking Technologies. * Experience in debugging platform issue with i2c, i2c trace analyzers, PCIe. * Knowledge of X86, ARM assembly code. * Motivated self-starter with good communication and organizational skills, with demonstrated ability to develop and deliver superior products in a cross-functional team environment under aggressive schedules. * Knowledge and experience of micro code and forwarding, datapath plus. * Knowledge and experience of DPDK is plus.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: FPGA Design. Experience:3-5 Years.

Develop and support the Fidessa-based Cash Equities order management and execution platform; enabling full trade lifecycle processing across global markets. ResponsibilitiesSupport high-throughput order management systems integral to equities tradingDesign and implement scalable; fault-tolerant solutions using Tcl/Tk and PythonCollaborate with trading desks and global tech teams across major financial hubsContribute to DevOps automation; CI/CD; and production stabilityMust-Have SkillsStrong communication in a fast-paced; front-office trading environmentStrong understanding of equities trading; market microstructure; and data normalizationTcl/Tk scripting; Primary Skills OA protocol; and reliable data stream architectureUnix; Python; and Sybase DB experienceHands-on with CI/CD; monitoring; and troubleshooting toolsNice-to-HaveJava; MongoDB; Solace; KafkaExperience with streaming data and real-time messagingStrong problem-solving and design thinking in capital markets context

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Design Planning. Experience: 1-3 Years.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. You thrive in a collaborative environment and are excited to work closely with global teams on the latest technology nodes. You have a strong understanding of semiconductor device physics and digital design, and you possess a solid foundation in CMOS fundamentals. Your familiarity with Unix/Shell/Python/TCL is an added advantage, and you are eager to leverage these skills to contribute to innovative projects. Your attention to detail and problem-solving abilities make you an ideal candidate for this role. What You’ll Be Doing: Designing and developing physical IP such as SERDES, DDR, and/or Memory as part of the Logic Libraries team. Collaborating with global teams to implement and optimize layout designs on the latest technology nodes. Utilizing your understanding of CMOS fundamentals to ensure high-quality and efficient design processes. Employing Unix/Shell/Python/TCL scripting to automate and enhance design workflows. Conducting design reviews and providing feedback to improve overall design quality and performance. Staying updated with the latest industry trends and technological advancements to ensure cutting-edge designs. The Impact You Will Have: Contributing to the development of high-performance silicon chips that power a wide range of applications. Enhancing the efficiency and reliability of physical IP design processes. Supporting the advancement of semiconductor technology through innovative layout designs. Collaborating with global teams to achieve project milestones and deliver high-quality designs. Improving the overall performance and functionality of Synopsys' technology solutions. Driving the continuous technological innovation that shapes the future of the industry. What You’ll Need: Strong understanding of semiconductor device physics and digital design principles. Solid foundation in CMOS fundamentals. Experience with Unix/Shell scripting and familiarity with Python/TCL. Proficiency in layout design and development of physical IP. Ability to work collaboratively with global teams and communicate effectively. Who You Are: Detail-oriented with strong analytical and problem-solving skills. Innovative and eager to stay updated with industry trends and advancements. Collaborative team player with excellent communication skills. Proactive and able to manage multiple tasks effectively. Passionate about semiconductor technology and its applications. The Team You’ll Be A Part Of: You will be part of the Logic Libraries team, a group of dedicated professionals focused on designing and developing high-performance physical IP. This team collaborates with global counterparts to implement the latest technology nodes and deliver cutting-edge solutions. Together, you will drive the innovation that powers the future of semiconductor technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI HVL Verification. Experience: 3-5 Years.

ASIC DFT Engineering Technical Leader :: Design for testability, JTAG, Scan and BIST :: Exp 8+ yearsDFT Engineering Technical Lead Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Prior experience working with Gate level simulation, debugging with VCS and other simulators. Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Prior experience with Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis Past experience with Post silicon validation using DFT patterns.