1282 System Verilog Jobs - Page 45

Job Category: Design Verification Job Type: Full Time Job Location: Bangalore Requirements: Bachelor s / Master s degree in Electrical Engineering or Computer Science with 6+ years of relevant experience Verilog / System Verilog based verification experience at Subsystem and Full chip level. Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols. Experience with System Verilog Assertions with industry standard tools a plus Experience with SOC bot flow, clocking and platform bring up in Emlators or Silicon Desired Experience with Low Power Verification and power management flows. Experience with RTL, GLS level simulations Knowledge and experience working on PCIE/Ethernet and other HSIO desired Experience in UVM/OVM based methodology Development. Responsibilities: Be part of a team to verify complex system on a chip designs. Interact with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using UVM/Sytem Verilog Create complex C/SV tests using reusable test libs Team player and mentor who is self-driven, motivated and guides a team of junior engineers Responsible for quality and timeliness of the team output

Job Category: Design Job Type: Full Time Job Location: Bangalore About Us: Mettlesemi Systems and Technologies Pvt Ltd, based in Bengaluru, specializes in providing embedded systems, silicon solutions and related services. We have strong partnerships with top oplayers in the Semiconductor and Embedded Systems domain, across product development and prototyping. The Role: Mettlesemi is looking for exceptional engineers and engineering leaders to join our SOC development team to develop cutting-edge products within disruptive system architecture. You will have the oppertunity to work on the latest technologies in silicon chip design within a dynamic, open, and fast-peaced environment and develop the next generation of chips based on revolutionary architecture for our top-notch clients. Key Responsiblities: We are looking for talented Senior engineers to join our top-tier teams and participate in design and verification activities working on next-generation products, starting from the identification and definition of project requirements, architecture, and feature development. As a Design Engineer and integral part of the project team, your responsibilities will encompass the development of intricate Microarchitecture, Logic Design, Synthesis, Timing Closure, and Formal Verification using Formality. Collaboration with the Design Verification Team, the DFT Team, the Physical Design Team and other stakeholder teams will be a key aspect of your role. This presents a unique opportunity for you to make a significant impact across the entire product lifecycle. In this role, you will work in a team developing SoCs to be deployed in a range of products/applications. You will integrate industry-standard and custom hardware IP and subsystems into SoCs and will work closely with System Architects, SoC architects, IP developers, and physical design teams to develop SoCs that meet the power, performance, and area goals for these products/applications. BASIC QUALIFICATIONS 6+ years of experience in chip design. 5+ years or more of practical semiconductor design experience. Proficiency in Verilog/System Verilog. Fluent in scripting languages (TCL, Python). BE degree in Computer Engineering/BS Computer Science/Electrical Engineering. Excellent verbal and written communication skills. Strong collaboration and teamwork skills, ability to contribute to diverse and inclusive teams. PREFERRED SKILLS/EXPERIENCE Experience with the full SOC cycle Synthesis/STA/CDC/Lint. Experience with successful tape-outs of complex, high- volume SoCs in advanced design nodes. Experience with Design Automation. Experience in Designing protocols such as AMBA, LPDDR, DDR4 Strong working knowledge of Network on Chip (NOC), Coherent, and non-Coherent fabrics.

AMD is looking for a talented, self-driven and motivated engineer to technically lead AIG s Simulation Modeling projects working on AMD s XDNA (AI Engine) architecture and the Vitis AI family of software tools. The XDNA is an industry leading architecture in terms of performance per watt and is used in AMD s client and embedded devices as the primary engine for Machine Learning workloads. It is the hardware engine behind Windows Co-pilot on AMD devices. The team provides a fast-paced environment offering each of its members immense opportunity to interact with a wide variety of people including from other organizations like hardware designers, marketing, support, and even direct customer interaction, and truly learn and grow their skills and capabilities. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated technical issues to resolution. They should have demonstrated ability to identify technical problems, explore and propose viable options, and apply technical solutions. They should be able to excel in a global team environment with strong verbal and written communication skills. . KEY RESPONSIBILITIES: Vitis AI is AMD s primary SDK that enables users to compile and run their ML models on the XDNA architecture. As a senior member of this high-performance team, the selected candidate will have responsibility to model the XDNA architecture in terms of functionality, accuracy and simulation speed. Candidate will work with compiler, runtime/driver teams to bring up latest AI models like CNNs, Transformers, StableDiffiusion, NLPs etc. on the XDNA simulator. This is a crucial part of AMD s shift-left strategy for the successful bring up of new devices and day 0 enablement of models. Candidates would develop a deeper understanding of the various ML models, and how they are executed, identify performance bottlenecks and enable faster development. PREFERRED EXPERIENCE: Minimum 10 years of relevant work experience. Strong background in C++ based development and debug, dealing with multi-threaded infrastructure and performance optimization Experience in creating cycle accurate modeling of IPs in C++ or SystemC / TLM. Understanding of SoCs, and bringing up of software stack from driver to application on simulation model. Understanding hardware metrics like latency/throughput on any sub-system, and what changes impact those metrics. Experience in software development environment on both Linux and Windows is required. Experience in technologies like Virtual Platforms, SystemC/QEMU models, Emulation platforms, Hw/Sw co-design, and Performance analysis is desired. Familiarity with hardware languages like VHDL, Verilog and System Verilog for simulation using tools like Modelsim, VCS, Questa Sim is highly desired. ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years"™ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. This position involves System Verilog real number modeling and functional verification of blocks involved in WAN, GPS radios for 5G products. Roles and responsibilities include: Understanding device functionality, building verification plan, functional Modeling of analog blocks in System Verilog, running and debugging testcases on a large mixed-signal SOC on RTL and Gate Level Netlists. Setting up and running AMS testbenches for RFIC modules. Working with SPICE/Spectre simulators and digital simulators (co-simulation). Analysis and debug Analog circuits. UVM/SV based Testbench creation, verification, creating self-checking tests, regression, debug, coverage analysis, bug tracking Scripting using PERL/Python/Shell to automate day to day verification tasks Working with Analog and Digital design environments like Cadence ncsim, simvision, virtuoso. Working in a fast paced environment with Analog, Digital design/DV, DFT engineers to ensure complete SoC verification Post silicon bringup support Minimum Qualifications Bachelor's degree in Electrical Engineering or Computer Engineering or related field, Masters preferred 2+ years ASIC design, verification, or related work experience Preferred Skills Experience in the following skills: Electrical circuit analysis Verilog, SystemVerilog, UVM Perl or Python Phaselock loops, ADCs, DACs, and serial programming interfaces Writing behavioral models of analog blocks including event driven simulator

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Required Qualifications Bachelor's degree /master"™s degree in Electronics & Tele Engineering, Microelectronics, Computer Science, or related field. 9+ years RTL Design/Hardware Engineering experience or related work experience. Skills/Experience Required Strong Domain Knowledge on RTL Design , implementation, and integration. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture & designing cores and ASICs. Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. Exposure in scripting (Pearl/Python/TCL). Strong debugging capabilities at simulation, emulation, and Silicon environments. Collaborate closely with cross-function team located in different time zone to research, design and implement performance and power management strategy for product roadmap. Good team player. Need to interact with the other teams/verification engineers proactively. Responsibilities Design and lead all Front-end design activities for Display Sub-system that deliver cutting edge solution for various Qualcomm business unit like VR, AR, Compute, IOT, Mobile. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks. Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation. Support SoC team to integrate Display Sub-system IP solution into various SoC chips and front-end design flows. Work closely with system/software/test team to enable the low power feature in wireless SoC product. Evaluate new low-power technologies and analyze their applications to address requirements. Understand and perform block & chip-level performance analysis & identify performance bottleneck and provide required solution. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas: Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Excellent Design verification domain expertise of min 3 years upto 6 years. Develop test strategy, TB architecture and test plan for new IP"™s/new features Develop strategies for re-useable, scalable and enhance Sub system level verification environment Excellent C/System Verilog/Verilog skills to handle C based TB environment Strong skills in debug, post silicon debug-failure re-creation and root cause analysis Scripting proficiency - PERL, Python, for developing applicable automation AMBA, AXI bus protocols Power intent verification, GLS etc. Capable of communicating effectively with all stakeholders across the globe Capable of seeding a new team for new IPs, able to hire and expand the team in expertise and efficiency Capable of mentoring the team members for their career growth, maintaining diversity in the team, collaborating with other leads and managing multiple parallel projects Take initiatives to enable various ideas for improving efficiencies. Good to have Image Processing, DSI/DP/HDMI Protocols Good knowledge of new methodologies, flows and tools to be incorporated. Formal Verification

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: QCT's Bangalore Wireless R&D HW team is looking out for experienced Wireless Modem HW model developers to work on Qualcomm"™s best in class chipsets in modem WWAN IPs Roles and Responsibilities You will be contributing to flagship modem core IP development covering 5G(NR) & 4G (LTE) technologies. You will be part of team defining and developing next generation multi-mode 5G modems. You will be working on development and verification of HW models of modem core IP. The models are developed on C++/SystemC platform and used as golden reference for RTL verification and pre Silicon FW development ( virtual prototyping). The candidate must be well versed with C++ and should have good exposure to SystemC and/or System Verilog and/or Matlab. The candidate must have ability to understand HW micro-architecture & its modeling abstraction. Working knowledge of physical layer of wireless technologies like NR,LTE , WLAN, Bluetooth is highly desired. Expertise on digital signal processing and working experience on HW modeling and/or RTL design/ verification of IP are preferred. Candidates with SW/FW background on wireless IP can also apply. Candidates with strong technical knowhow on non-wireless DSP based HW IPs ( with Design / Verification/ Modeling skills) will also be considered. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly skilled and experienced SoC Management IP Design lead to join our team. This position requires overseeing the development of all SoC Management IPs primarily Debug and Timer IPs, which includes creating micro-architecture specifications, IP design and verification. The ideal candidate will have a strong background in IP development and SoC Management Architecture, with a focus on both technical leadership and management responsibilities. IP Design, Verification and Delivery SoC and Platform Architecture Development Key Responsibilities Leadership and Management Lead and manage the development of SoC management IPs, Primarily Debug and Timer IPs IP Design, Verification and Delivery Provide technical leadership and guidance to the IP development team. Oversee the entire lifecycle of IP development, from concept to implementation and validation. Collaborate with cross-functional teams to ensure seamless integration of IPs into SoC designs. Technical Expertise Experience of RTL design for complex SoC development using Verilog and/or SystemVerilog Experience with Arm-based designs and/or Arm System Architectures Drive the architecture and design of SoC Management IPs. Ensure the IPs meet performance, power, and area requirements. Stay updated with the latest industry trends and technologies in SoC management and IP development. Troubleshoot and resolve complex technical issues related to IPs. Collaboration and Communication Work closely with other engineering teams, including SoC design, verification, and validation teams. Foster a collaborative and innovative work environment. Communicate effectively with team members, management, and external partners. Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in SoC Management IP development, including debug and timers IPs. Strong technical leadership and management skills. Excellent understanding of SoC architecture and design principles. Strong problem-solving and analytical skills. Excellent communication and interpersonal skills. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. About The Role Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications Master's/Bachelor"™s degree in Electrical Engineering, Computer Engineering, or related field. 8+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production. As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs. This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug. You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness. Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability from early DFT architecture planning to high-volume silicon bring-up and yield ramp. Key job responsibilities Key job responsibilities Lead development & implementation of DFT architecture including system level DFT for a full chip Write and guide others in writing design flow and project documentation. Own DFT planning, milestone tracking, and cross-functional checklist reviews. Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists. Review and sign-off SoC level DFT mode timing closure using static timing analysis Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon Keep informed on and introduce new technology into Design-for-Test process as appropriate. Education: BS/BE or MS/ME in Electrical Engineering, Computer Engineering, or related field. Experience: 15+ years in SoC/ASIC DFT, including 3+ years Leading DFT. Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production. DFT Architecture Expertise: Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including: Scan architecture, compression, and ATPG implementation for high fault coverage and test quality. MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration. IEEE 1149.x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures. DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths. RTL and gate-level debug, including mismatch triage and simulation correlation. Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation. Tool Proficiency: Deep hands-on experience with Tessent / Industry Std EDA tools, including: IJTAG ICL extraction and PDL modeling. DFT logic insertion, pattern generation, and diagnostics. Design Background: Experience in writing verilog/system verilog RTL related to DFT logic design. ATE Test Readiness: Lead DFT-to-ATE handoff, including: Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets. Pattern validation, format conversion, and debugging across wafer sort and final test. Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements. Silicon Debug: Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis. Automation Skills: Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl. Collaboration: Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing. Execution Excellence: Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success. Leadership: Led multi-site/global DFT teams, mentoring engineers and managing design reviews. Drove design-for-test planning in collaboration with customers or design services partners. Technical Depth: Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies. Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues. Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is seeking a motivated memory subsystem architects with great analytical skills and a deep understanding of system architecture and performance, to work with a team to model, debug and analyze performance issues in the Memory subsystem. What you will be doing: Contribute to advancing GPU Architecture and Simulators, GPU testing infrastructure, metrics, and/or compilers. Performance modeling and simulation of features to improve memory system efficiency. Develop test plans and testing infrastructure. Debug tests on architecture simulators. Performance analysis/ bottleneck analysis of sophisticated, Memory subsystem units and features. Work on hardware models of different levels of extraction, including performance models, RTL test benches and emulators to find performance bottlenecks in the system. Working with various multi functional teams like ASIC design and verification.. What we need to see: Master/Bachelors degree in Electrical Engineering, Computer Science, Computer Engineering or related field (or equivalent experience). 5+ years experience dealing with system level architecture and performance issues. Strong programming ability in C, C++. Exposure to Verilog/System Verilog is a strong plus. Good understanding of Memory subsystem architecture, caches , MMU, memory controller, NOC / interconnects, computer architecture. Debugging and analysis, including use of RTL dumps to debug failures. Exposure to performance simulators, cycle accurate/approximate models or emulators for pre-silicon performance analysis is a plus. Strong communication and interpersonal skills are required along with the ability to work in a dynamic, product oriented, distributed team. Ways to stand out from the crowd: Knowledge of the memory system, caching, interconnects, DRAM controller, Memory management unit, performance modeling and analysis. Widely considered to be one of the technology world s most desirable employers. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, perform essential job functions, and receive other benefits and privileges of employment. #LI-Hybrid

Design verification SOC Verification UVM, OVM Verilog, System Verilog Test Bench, Test cases

"> Search Jobs Find Jobs For Where Search Jobs R&D Engineering, Staff Engineer - IP Verification Noida, Uttar Pradesh, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 7271 Date posted 02/24/2025 Share this job Email LinkedIn X Facebook Experience : 5yrs to 10 years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective Locally should be to be "go-to" person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

"> Search Jobs Find Jobs For Where Search Jobs R&D Engineering, Staff Engineer (VIP verification) Noida, Uttar Pradesh, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 8828 Date posted 02/24/2025 Share this job Email LinkedIn X Facebook Experience : 5yrs to 12 years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be "go-to" person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

"> Search Jobs Find Jobs For Where Search Jobs SOC Engineering, Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10321 Remote Eligible No Date Posted 26/03/2025 Alternate Job Titles: SoC Verification Engineer Staff SoC Verification Specialist Senior SoC Verification Engineer We Are: At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world s most advanced technologies for chip design and software security. If you share our passion for innovation and SoC Design, we want to meet you. You Are: You are a highly skilled and experienced SoC Verification Engineer with a strong background in electronics and a passion for innovation. You possess a deep understanding of processor-based SoC level verification, including experience with Verilog, System Verilog, and UVM mix environment. Your hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (such as Synopsys VIPs) sets you apart as a leader in your field. With strong problem-solving, analytical, and debugging skills, you thrive in dynamic and challenging environments. You are an excellent communicator and collaborator, capable of mentoring junior engineers and working effectively with cross-functional teams. What You ll Be Doing: Understanding design specifications, defining verification scopes, developing test plans, tests, and verification infrastructure. Implementing and analyzing System Verilog assertions and coverage (code, toggle, functional). Collaborating with other verification team members to develop and execute verification test cases. Leading and mentoring junior engineers, helping them debug complex problems. Working with architects, designers, and pre- and post-silicon verification teams to accomplish tasks. Adhering to quality standards and best verification practices. Ramping up on new verification tools and methodologies using Synopsys products to enable customers. Developing innovative solutions to problems independently. Setting task-level goals and consistently meeting schedules. Collaborating with other Synopsys teams, including BU AEs and Sales, to develop and deploy tool and IP solutions. The Impact You Will Have: Ensuring the correctness and reliability of complex SoC designs. Enhancing the efficiency and effectiveness of verification processes. Mentoring and developing the skills of junior engineers. Contributing to the successful delivery of high-quality SoC products to market. Driving innovation in verification methodologies and tools. Strengthening Synopsys position as a leader in the semiconductor industry through your technical expertise. What You ll Need: B.E/B. Tech/M. E/M. Tech in electronics with 4-8 years of experience in the verification domain. Experience in IP level or SoC level verification. Proficiency in processor-based SoC level verification, including Verilog, System Verilog, and UVM. Hands-on experience with verification tools such as VCS and waveform analyzers. Experience with third-party VIP integration (e.g., Synopsys VIPs). Proficiency in UVM, C/C++, and System Verilog verification languages. Understanding of AXI-AMBA protocol variants. Experience with scripting languages (shell, Makefile, Perl). Strong understanding of design concepts and ASIC flow. Strong problem-solving, analytical, and debugging skills. Experience with ARM core verification and ARM-based technologies. Experience with USB, PCIe, and MIPI protocols. Excellent communication skills. Who You Are: An innovative thinker with a passion for technology and verification. A collaborative team player who excels in dynamic environments. An excellent communicator who can articulate complex ideas clearly. A problem solver with a keen eye for detail and quality. A mentor and leader committed to developing the skills of junior engineers. A lifelong learner dedicated to staying at the forefront of technological advancements. The Team You ll Be A Part Of: The Systems Solutions Group (SSG) delivers tool, methodology, architecture, design creation, design verification, and physical implementation expertise to enable leading-edge customers to complete their most challenging SoC design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. Our customers develop SoCs for high-performance computing, automotive, aerospace & defense, and more. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!