Expertise and strong hands-on experience in RTL design using System Verilog or VHDL Digital system architecture, Processor subsystem architecture and block definition,complex SoCs, RTL design quality analysis – Lint, CDC, RDC,DFT,simulation,
Experience with OVM/UVM/VMM/Test Harness, developing assertions, checkers, coverage, and scenario creation.,min 2 to 3 SoC Verification projects.developing test and coverage plans, verification environments, and validation plans,