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Advanced Micro Devices, Inc
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MTS IP Verification Engineer

MTS IP Verification Engineer

Advanced Micro Devices, Inc

5 - 15 years

35 - 40 Lacs

Hyderabad

Posted:5 days ago| Platform:

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Skills Required

Graphics ASIC VLSI SOC VMM System verilog PCIE Gaming IPS Recruitment

Work Mode

Work from Office

Job Type

Full Time

Job Description

MTS SILICON DESIGN ENGINEER

THE ROLE:

The verification team at AMD is looking for a Member of Technical Staff to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.

THE PERSON:

You have a passion for modern, complex digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
Interact with architects and design engineers to create a comprehensive verification testplan
Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
Debug tests with design engineers to deliver functionally correct design blocks
Identify and write coverage measures for stimulus quality improvements
Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

PREFERRED EXPERIENCE:

Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
Strong understanding of different phases of ASIC and/or full custom chip development is required.
Experience in block level NOC (Net work on Chip) verification is a plus.
Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.
Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus.
Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

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MTS IP Verification Engineer