Staff / Senior Staff ASIC Design Engineer

Job Title:

Company:

About Cyient Semiconductor:

ASIC, SoC, and Mixed-Signal design services

Role Overview:

highly skilled ASIC Design Engineer (Staff / Sr. Staff level)

latest technology nodes

Key Responsibilities:

• Perform

  RTL coding and integration

  for complex SoC/ASIC blocks using Verilog or System Verilog.
• Develop

  micro-architecture specifications

  , interface documents, and design documentation.
• Own the complete RTL design flow from specification to synthesis handoff.
  
• Perform

  RTL linting, CDC, RDC, and design quality checks

  .
• Collaborate closely with

  verification, synthesis, physical design, and DFT teams

  to ensure high-quality design signoff.
• Develop and maintain

  timing constraints (SDC)

  for block and top-level synthesis.
• Drive

  synthesis, timing analysis, and constraint validation

  to achieve optimal PPA (Performance, Power, Area).
• Create and enhance

  scripts (TCL/Perl/Python)

  to automate design and synthesis workflows.
• Contribute to design reviews, root-cause analysis, and design closure activities.
  
• Mentor junior engineers in design practices, coding standards, and tool usage.
  

Required Skills and Experience:

• 610 years

  of hands-on experience in

  ASIC / SoC RTL Design

  .
• Strong proficiency in

  Verilog / SystemVerilog RTL coding

  .
• Excellent understanding of

  synthesis flow

  ,

  timing closure

  , and

  constraint development (SDC)

  .
• Hands-on experience with

  EDA tools

  such as Synopsys Design Compiler, Fusion Compiler, or Cadence Genus.
• Knowledge of

  static timing analysis (STA)

  concepts and design optimization.
• Experience in

  developing and validating design constraints

  .
• Proficiency in

  scripting languages (TCL, Perl, Python, Shell)

  for automation.
• Strong understanding of

  SoC architecture, clock/reset domains, and power management techniques

  .
• Good analytical and problem-solving skills with attention to design quality.
  
• Excellent communication and teamwork skills.
  

Good to Have:

• Exposure to

  DFT insertion, floorplanning constraints

  , or

  timing ECO

  flows.
• Knowledge of

  low power design techniques (UPF/CPF)

  .
• Familiarity with

  lint/CDC tools

  (SpyGlass, VC-Lint, Questa CDC, etc.).
• Experience in

  high-performance or low-power ASICs

  at advanced nodes (e.g., 7nm, 5nm).

Education:

• B.E./B.Tech/M.E./M.Tech

  in Electronics, Electrical, or VLSI Design Engineering.