Staff Engineer

To work as a Frontend engineer and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects. Job Description Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis . Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirements. Your Profile Strong fundamentals and experience in Synthesis and STA domains. Write and implement block level and top-level timing constraints for Synthesis Optimize designs for power, performance, and area, and meet design goals. Knowledge on Power analysis and PT-PX flow. Understanding of DFT flows, including scan insertion. Write and evaluate Test/DFT mode timing constraints. Thorough with Logic Equivalence Check debug capability. we'll known about UPF concepts and Low Power Checks at block and full chip level. Defining and verification of STA constraint for Functional and Test/SCAN Modes. Defining PVT s corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow