926 Sta Jobs - Page 3

We are seeking a highly experienced Senior Physical Design Engineer with 8+ years of experience in block-level and full-chip physical implementation. The candidate should be proficient in physical design flows and methodologies for advanced technology nodes. Key Responsibilities: Drive physical implementation from RTL to GDSII (floorplanning, placement, CTS, routing) Perform timing analysis, congestion analysis, and physical verification (DRC/LVS) Optimize for performance, power, and area (PPA) Collaborate closely with RTL, STA, DFT, and package teams Own signoff checks (IR drop, EM, Antenna, Crosstalk, etc.) Support tape-out and silicon validation activities Requirements: 8+ years of experience in physical design implementation and signoff Strong hands-on experience with tools like ICC2, Innovus, Primetime, RedHawk, Calibre Solid understanding of timing closure, IR/EM analysis, and power optimization Experience with advanced nodes (7nm, 5nm, etc.) is a plus Good scripting skills (TCL, Perl, Python) for automation Strong communication and teamwork skills

Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Master's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure.

This role does design and layout of complex VLSI (very large scale integration) circuits using graphic editing tools in cutting edge technological nodes. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-7 Years of relevant experience in Memory Layout design for blocks like Caches, CAMs, Register files, multiport register Files, Compilers etc.Should be in a position to work hands on on memory IPs, help generate and curate new ideas for layout designing, innovate new ways of layout designing, bring leadership into work and have growth mindset and have openmindedness to automation ideas; Excellent communication skills to be able to work with crosssite designers, EDA for development and curation of new tools needed for work. Should be able to understand various memory architechtures, experience in bit cells layouts, compiler layout design; Should have hands on experience in Finfets, GAA etc. Should have had experience in technology nodes below 7nm; LVS, DRC, Antenna, DFM, EM, IR, Methodology check debugging and fixing is a must; Leadership to drive collaborative initiatives with cross teams; SRAM designing experience is an added advantage Preferred technical and professional experience Scripting to ease deliverables is an added advantage. Automation skills in PERL, Python , and/or TCL

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal methodology, Knowledge of HDLs (Verilog, VHDL, SV), Good programming skills in python, processor core u-arch skills Exposure in developing testbench environment, debugging and triaging fails. Good communication skills and be able to work effectively in a global team environment. Drive verification coverage closure, lead verification team. Drive complex scenarios, participate in High level design discussions. Track record in leading teams. Preferred technical and professional experience Writing test plans, building random / exhaustive formal verification environment, functional and coverage analysis and debug. Good understanding of the Server System

THE ROLE: As the one of the design leads of the Programmable Clock & Methodologies team in India for AMD's Adaptive-Embedded Computing products, you will be responsible for driving the development of clocking solutions that meet the high standards of AMD's AECG products. This will involve leading a team of highly skilled engineers in India, as well as collaborating with the global Clock team of experts at the San Jose office, inventing and implementing original solutions, addressing challenging clock problems in some of the industry's largest and most complex SOCs. Every new Adaptive SOC brings a new set of programable Clock challenges with their latest system and functional architectures and their adoption of new semiconductor and packaging technologies. The Global Clock team works closely with functional Architecture, Programable fabric, Integration and SW teams to craft and implement new clock solutions, including new architectures, Clock IPs and development of new tools, flows & Methodology. THE PERSON: You will lead by bringing people together and drive towards consensus, decisions, and results. Working independently, you will convert high level concepts down to tangible specifications that can be implemented efficiently. You should enjoy collaborating with engineers with their diverse skillsets and bring their expertise to bear on solving challenging Programable Clock problems. KEY RESPONSIBILITIES: Lead floor-planning, placement, routing, custom clock tree design, and optimization. Expert knowledge and hands-on experience of the entire backend and adjacent flows, including synthesis, Floor-planning P&R, clocking, timing closure, power and IO planning Perform all aspects of design flow from feasibility analysis, logic synthesis, FP, place and route, FEV, power, timing, quality checks, and design closure. Collaborate with design, Physical design, IT/infrastructure teams to ensure successful CAD flow all the way from IP design to SoC/3DIC design. Developing Programable global Clock distribution methodologies, optimizing Clock - Skew, Signal integrity and power integrity issues for AMD's next generation of programmable product families. Large Scale Block to Block Clock timing analysis, within the Die & Die to Die Clock interposer crossing. Deep analysis of timing paths to identify and debug key issues. Collaborate with functional IP teams (RTL, Ckt, physical design, Full Chip Timing, Integration) during the implementation and qualification of a growing number of programable Clock IPs. PREFERRED EXPERIENCE: You should have a deep understanding of clocking methodologies and experience in leading teams to deliver complex projects. Workingknowledge of Programable clocking is a plus. Strong working knowledge in all aspects of Physical Design and Advanced Packaging (Professional Experience: 10+ years of hands-on experience in physical design and verification, with a proven track record in chip-level PNR and successful tapeouts of complex SoC designs). You should be an expert in the development of clocking solutions and have the ability to work effectively with global teams (USA & India) to ensure that on time product delivery with high quality is met. Strong Clock fundamentals (Clock switching and gating, synchronization, Clock skew balancing, Jitter, Fmax, DCD and CDC analysis). Familiarity with test, debug, yield, post-Silicon Validation & Characterization is a plus. Working experience of Package level Clock SIPI is a plus. Proficient in STA and methodologies for timing closure and have a good understanding of noise, cross-talk, Aging and OCV effects, among others.Defined timing/SDC and placement constraints for IPs. Familiar with circuit modeling, including SPICE models, and worst-case corner selection. Familiarity with Verilog and system Verilog for design. Additionally, you should be a skilled communicator, able to provide technical guidance and mentorship to junior team members to help them develop their skills and advance their careers. ACADEMIC CREDENTIALS: Bachelor or master degree in computer engineering/Electronics or Electrical Engineering with 8-12+ years of exp.

THE ROLE: The focus of this rolewill involve driving the physical design flow from timing through final sign-off, collaborating closely with cross-functional teams to meet stringent power, performance, and area (PPA) targets on SerDes PHY IPs. THE PERSON: As a senior member of the SerDes IP Physical Design (PD) team, your primary responsibility will be overseeing the timing and implementation of crucial PHY IPs. You will focus mainly on the Design-For-Test (DFT) logic and its integration with operational mode logic. A strong grasp of DFT concepts is advantageous, as it provides a comprehensive perspective to achieve design specifications. This role demands profound technical expertise in physical design tools and methodologies, along with the capability to lead and mentor a group of physical design engineers in future. KEY RESPONSIBILITIES: Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively. Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation. Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for DFT. Identify opportunities to optimize clock skew and insertion delay across various corners and modes. Evaluate the clock/reset-domain-crossing (CDC/RDC) issues at the netlisting stage and offer feedback on design fixes or establish waivers if the changes are not feasible. Implement power-saving strategies, such as power gating, multi-voltage domains, and clock gating, to meet low-power objectives while preserving performance standards. Create and refine custom scripts using Tcl, Perl, or Python to enhance workflow efficiency and streamline physical design operations. Mentor and support junior physical design engineers, disseminating best practices and providing technical guidance to elevate team proficiency and performance. PREFERRED EXPERIENCE: Over 8-10+ years of professional experience in constraints generation, synthesis, static timing analysis (STA), and IP-level timing and physical design, with a preference for high-performance SerDes designs. Proven ability in timing analysis, convergence, timing ECOs, and .lib generation. Experience with STA closure on PHYs & understanding the timing requirements across digital and analog macro interfaces is a plus. Proficient in physical design tools such as Synopsys ICC2, Primetime, and the ASIC design flow. Skilled in scripting with Tcl, Python, or Perl to automate and streamline physical design tasks. Excellent problem-solving, leadership, and communication skills and values team culture. Capable of thriving in fast-paced environments and managing multiple projects simultaneously. ACADEMIC CREDENTIALS: Master's degree in computer engineering/electrical engineering

We are looking for an experienced Physical Design Engineer responsible for complete physical design and implementation, including floor planning, P&R, timing closure, power and noise analysis, and back-end verification across multiple advanced node projects. Key Responsibilities: Perform chip floor planning, power/clock distribution, P&R, and chip assembly Achieve timing closure and conduct power/noise analysis Manage complete netlist to GDSII flow for ASIC designs Handle synthesis, STA, and physical implementation of hard-macros and/or full-chip designs Collaborate across teams to ensure successful backend design and delivery Utilize low-power design techniques and apply them effectively in backend flow Develop and maintain automation using scripting languages

As a Design Verification Engineer at our Hyderabad location, you will be responsible for verifying the design of industry-leading products, such as Graphics DDR7. With 5-7 years of experience in SV, UVM, Test Bench Development, Soc, Full-chip verification, and memory experience, you will play a crucial role in ensuring the quality and reliability of our products. Your primary responsibilities will include Verilog simulation, UVM methodology implementation, and full-chip verification. Familiarity with memory interfaces is highly preferred. Additionally, you will have the opportunity to work on projects involving GLS, STA, Python knowledge, and circuit characterization. We are looking for someone with a quick learning ability, a positive attitude, and strong technical skills in system Verilog and UVM. Your educational background should include a bachelor's degree, and any experience in static timing analysis, GLS, and Python automation for test bench development will be advantageous. Strong communication skills are essential for this role, as you will be required to effectively convey complex technical concepts to your peers. A proactive learner with strong analytical and problem-solving skills will thrive in this dynamic environment. If you are a local candidate and an immediate joiner with a passion for design verification and a desire to work on cutting-edge products, we would love to hear from you. Join us in our mission to deliver high-quality products to our customers and make a significant impact in the industry.,

As a Senior Physical Design Engineer, you will be responsible for leading the Netlist-to-GDSII implementation process on advanced submicron technology nodes. Your expertise in utilizing industry-standard EDA tools and your understanding of timing closure and physical verification will be crucial for this role. Your key responsibilities will include driving the entire Netlist-to-GDSII flow, which involves tasks such as floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. You will also be required to conduct Static Timing Analysis (STA) to ensure timing closure across all design corners, as well as execute power integrity and physical verification checks (LVS, DRC). Collaboration with cross-functional teams including RTL, STA, packaging, and DFT will be essential to successfully handle complex designs on 28nm and below technology nodes. To excel in this role, you must possess strong hands-on experience with tools such as Synopsys/Cadence Innovus, ICC2, Primetime, PT-PX, and Calibre, along with a solid understanding of Physical Design Methodologies including Floorplanning, Placement, CTS, Routing, and STA. Proficiency in timing constraints and closure, Tcl/Tk/Perl scripting, and working with submicron nodes (28nm and below) are also essential skills required for this position. While not mandatory, familiarity with Fusion Compiler, a broader understanding of signal and power integrity, as well as experience in workflow automation and tool scripting would be considered advantageous for this role. If you are excited about the prospect of taking on this challenging and rewarding opportunity, we encourage you to submit your resume to hemanth@neualto.com or spoorthy@neualto.com to express your interest.,

You will be part of a highly skilled and challenging high-speed parallel PHY design team, working on DDR, LPDDR, and other similar projects. Your responsibilities will include designing and developing high-speed interface PHY and its sub-blocks, such as high-speed data paths, analog calibration, training, IP initialization, low power control, test, and loopback functionalities. You will be accountable for various aspects of design and verification starting from specification to silicon, along with interface design for controllers and SoCs. Your active involvement in problem-solving and identifying opportunities for improvement will be crucial. Additionally, you will be mentoring and coaching other design team members on technical issues, collaborating closely with Analog designers to ensure a seamless interface between Digital and Analog circuits. Your skill set should include strong fundamental knowledge of digital design, Verilog, and scripting languages. Experience with micro-architecture and Asynchronous digital designs is required. Working knowledge of Synthesis, STA, Lint & CDC, DDR/LPDDR JEDEC protocol, DDR PHY designs, training algorithms, data path designs, domain transfer designs, APB/JTAG, and DFI is essential. The ideal candidate should have an M.S./M.Tech or BS/BE degree in Electronics. Micron Technology is a global leader in innovating memory and storage solutions, with a vision to transform how the world uses information to enrich lives. Micron's relentless focus on customers, technology leadership, and manufacturing excellence delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through the Micron and Crucial brands. Micron's innovations power the data economy, enabling advances in artificial intelligence and 5G applications from data centers to the intelligent edge, and across client and mobile user experiences. For more information about Micron Technology, Inc. and career opportunities, please visit micron.com/careers. To seek assistance with the application process or request reasonable accommodations, please reach out to hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and adheres to all applicable laws, regulations, and international labor standards.,

As a Senior FPGA Design Engineer at Prodigy Technovations in Bangalore/Bengaluru, you will have the opportunity to work on existing and next-generation Protocol Analyzers and similar products. Your role will involve contributing to the entire FPGA-based product development flow, from requirement analysis to final product testing in a lab environment. Your responsibilities will include architecture/micro-architecture design, Verilog logic implementation for targeted FPGA, and writing test benches to validate the design. You will collaborate closely with board design, software, testing, and lab teams to ensure the product meets customer requirements. Additionally, you will work with interfaces such as PCIe, GigE, MPHY/UFS, DPHY/CSI/DSI, USB, SD, eMMC, I3C/I2C, SPI/QSPI, among others. Qualifications: - BE/ME in Electronics from a reputed college, with a specialization in VLSI and Embedded Design being a plus. - 3 to 8 years of experience in designing and implementing FPGA-based solutions in Xilinx or Altera FPGA, preferably in FPGA-based product development. - Experience in System Design with Xilinx/Altera FPGA devices and relevant tools. - Proficiency in Verilog and/or VHDL coding. - Experience in synthesis, implementation, and using constraints to achieve timing requirements. - Knowledge of high-speed FPGA designs and Static Timing Analysis (STA) is advantageous. - Experience in building test benches for verification, board-level testing, and system debugging. - Familiarity with protocols like UFS, UniPro, USB, Ethernet, PCIe, I3C, I2C, SPI, QSPI, UART, JTAG, SPMI, RFFE, SD, eMMC. - Hands-on experience with FPGA debugging tools, oscilloscopes, and Logic Analyzers. - Strong problem-solving and debugging skills. If you are a motivated and experienced FPGA Design Engineer with a passion for product development and a strong background in FPGA technologies, we encourage you to apply for this exciting opportunity. Join our team at Prodigy Technovations and be part of creating cutting-edge solutions for top semiconductor companies.,

As STA engineer , the role would expect the candidate to have deployment of new features and or methodologies related to STA and ECO domain . Scope of the work would cover (but not limited to) STA flow/methodology development, continuous efficiency improvement, Flow development/Support for ECO convergence with tools in STA and ECO domain (PrimeTime, Tempus, Tweaker, PrimeClosure to name a few). There would be challenges for timing convergence at both block and Top level on cutting edge technology on high performance designs would have to be resolved for ensuring successful design tapeouts on time with high quality. Basic Hands-on on Scripting is a must to have for candidate. Specific skills & knowledge Bachelor or Master in Electronics Engineering and specialization in VLSI domain. 5-8 years of hands-on experience in SoC and IP level objectives on low geometry nodes (5/14/16/28/40nm). Experience in Synopsys Cadence tools, low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project Proven experience in delivering timing closure methodology of mixed signal SoC with high speed PHYs, IOs, PMU IP etc. closing analog / digital interfaces timing & signal integrity issues Experience in customizing flows & methodology to meet low power & area objectives of SoC and leading team to execute on time Ability to use scripting languages / automation of Physical Implementation methodology creation and deployment Should have proven experience in demonstrating strong technical leadership to deliver on commitment, anticipation of challenges, assertive communication and excellent team player. Excellent communication skills with proven experience in international relationships

Job Requirements Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills. Work Experience Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills.

Ansys is looking for Principal R&D Engineer - Implementation flow (physical synthesis / clock tree synthesis) to join our dynamic team and embark on a rewarding career journey Analyzing customer needs to determine appropriate solutions for complex technical issues Creating technical diagrams, flowcharts, formulas, and other written documentation to support projects Providing guidance to junior engineers on projects within their areas of expertise Conducting research on new technologies and products in order to recommend improvements to current processes Developing designs for new products or systems based on customer specifications Researching existing technologies to determine how they could be applied in new ways to solve problems Reviewing existing products or concepts to ensure compliance with industry standards, regulations, and company policies Preparing proposals for new projects, identifying potential problems, and proposing solutions Estimating costs and scheduling requirements for projects and evaluating results

Title: Physical Design Lead (PnR, STA) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Job Summary The individual will reports into the Design Methodology group and will be part of a team that is responsible for the creation of Design Methodology solutions for a wide variety of Technology nodes. Your role is focused on the development of Digital design enablement collateral to help GLOBALFOUNDRIES customers adopt the most advanced silicon technologies (12/14/22/28/40/55). Specific Responsibilities RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification Will be closely collaborating with EDA vendors and PDK to define, implement, customize, and qualify digital design flows Uses TCL, Python, Pandas and Google APIs to create automation for flow regressions, to collect and compare flow errors, warnings and key design metrics to ensure good quality PDK release and released flow backward compatibility to PDK Use reference flows to perform cross tool and PDK PPA benchmarking Define and generate design testcases to target and measure specific aspects of GLOBALFOUNDRIES PDK and technology changes Work independently in an international team, to drive project definition, execution, and delivery Perform all activities and responsibilities in safe and responsible manner and support all Environmental, Health, Safety, Security requirements and programs Required Qualifications Very good understanding of process technology, digital design, and digital implementation and analysis EDA tools and flows. Deep hands-on experience with digital implementation tools and flows (i.e. Synopsys ICC/ICC2, Cadence EDI/INNOVUS, or Mentor OlympusSoC) including RTL synthesis, Place and Route, parasitic extraction and static timing (Synopsys or Cadence) and physical verification (Mentor, Synopsys, or Cadence) using advanced technologies like 12/14/28 technologies Strong EDA tool scripting using TCL, Make and proficiency in Python programming language, data structures, functions and OOPs Strong communication skills within a global team and the ability to define and execute projects independently Bachelors/Masters degree in electrical or computer engineering fields with required + 15 years of relevant work experience Preferred Qualifications Low power design techniques and UPF (IEEE 1801) Understand liberty (.lib) formats (NLDM, CCS, ECSM, AOCV/POCV/LVF) Hands-on experience using version control software like Perforce. Java, SQL are also preferred. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Title: Physical Design Lead (PnR, STA) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Job Summary The individual will reports into the Design Methodology group and will be part of a team that is responsible for the creation of Design Methodology solutions for a wide variety of Technology nodes. Your role is focused on the development of Digital design enablement collateral to help GLOBALFOUNDRIES customers adopt the most advanced silicon technologies (12/14/22/28/40/55). Specific Responsibilities RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification Will be closely collaborating with EDA vendors and PDK to define, implement, customize, and qualify digital design flows Uses TCL, Python, Pandas and Google APIs to create automation for flow regressions, to collect and compare flow errors, warnings and key design metrics to ensure good quality PDK release and released flow backward compatibility to PDK Use reference flows to perform cross tool and PDK PPA benchmarking Define and generate design testcases to target and measure specific aspects of GLOBALFOUNDRIES PDK and technology changes Work independently in an international team, to drive project definition, execution, and delivery Perform all activities and responsibilities in safe and responsible manner and support all Environmental, Health, Safety, Security requirements and programs Required Qualifications Very good understanding of process technology, digital design, and digital implementation and analysis EDA tools and flows. Deep hands-on experience with digital implementation tools and flows (i.e. Synopsys ICC/ICC2, Cadence EDI/INNOVUS, or Mentor OlympusSoC) including RTL synthesis, Place and Route, parasitic extraction and static timing (Synopsys or Cadence) and physical verification (Mentor, Synopsys, or Cadence) using advanced technologies like 12/14/28 technologies Strong EDA tool scripting using TCL, Make and proficiency in Python programming language, data structures, functions and OOPs Strong communication skills within a global team and the ability to define and execute projects independently Bachelors/Masters degree in electrical or computer engineering fields with required + 15 years of relevant work experience Preferred Qualifications Low power design techniques and UPF (IEEE 1801) Understand liberty (.lib) formats (NLDM, CCS, ECSM, AOCV/POCV/LVF) Hands-on experience using version control software like Perforce. Java, SQL are also preferred. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia

Roles & Responsibilities: Be part of a team to verify or emulate/prototype complex system on a chip designs. Interact with design engineers to identify important verification scenarios. RTL Design / porting of ASIC RTL targeting FPGA prototyping and emulation platforms, such as Synopsys ZEBU, Cadence Palladium or Siemens Veloce Synthesis, PNR and timing analysis of RTL on industry standard prototyping and emulation platforms Qualification, Experience & Skills desired: Bachelor's degree in Electrical/Electronics Engineering with 5+ years of relevant experience, or masters degree in Electrical Engineering Skilled in FPGA design techniques, RTL Design, tools and processes. Minimum 5 years and above experience in digital design/verification, emulation/ FPGA prototyping and system validation. Verilog/SystemVerilog based verification experience at Subsystem and Full chip level. Experienced in transactor-based verification. Verification methodology like UVM/OVM knowhow is a plus. Knowledge of RTL language (e.g., VHDL, Verilog), in-circuit emulation, simulation acceleration and FPGA prototyping. Familiar with emulation/prototyping tools and methodologies. Real experience of mapping complex SOC design into multi-FPGA platforms/emulators and hands on experience with Synopsys ZEBU, Cadence Palladium, Siemens Veloce or HAPS A proven track record with emulation-based verification methodologies including ownership of a suitably complex emulation workflow environment. Well versed in model building for prototyping or emulation. Experience with STA/timing closure, wrapper creation, HDL simulation, synthesis, and memory modelling for prototyping/emulation. Working knowledge of Perl, Python & Shell scripts is a plus Experience with digital systems based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols. Experience with SOC boot flow, writing basic test cases, clocking and platform bring up in Emulators or Silicon desired Interested in and passionate about staying updated with tech trends. Excellent verbal and written communication skills to communicate issues, impact and corrective action.

Key Responsibilities Lead block-level PNR activities from floorplanning through final routing, ensuring robust physical implementation aligned with timing, power, and area goals. Drive power grid design and EM/IR-aware routing strategies to ensure block-level power integrity and reliability. Collaborate closely with timing closure engineers to resolve physical design bottlenecks impacting timing and signal integrity. Manage and optimize physical verification flows including DRC, LVS, antenna checks, and physical signoff. Automate PNR flows and develop scripts to improve productivity and design quality. Mentor and guide junior physical design engineers, fostering technical growth and best practices. Coordinate with cross-functional teams including RTL design, STA, verification, and backend integration to ensure seamless block-to-chip integration. Qualifications and Skills 8+ years of experience in physical design with a strong focus on block-level Place and Route (PNR) for complex SoC/IP subsystems, preferably at advanced technology nodes (16nm, 7nm, 5nm, or below). • Proven expertise in block-level physical implementation including floorplanning, placement, clock tree synthesis(CTS), routing, and physical verification (DRC/LVS). • Hands-on experience with industry-standard PNR tools such as Cadence Innovus, Synopsys ICC2, and Mentor Calibre. • Strong understanding of power grid design, EM/IRanalysis, signal integrity (SI), and reliability checks at the block level. • Experience in managing timing closure in coordination with STA teams, resolving congestion, and optimizing for power, performance, and area (PPA). • Proficiency in scripting languages (Tcl, Python, Perl) for flow automation and custom tool development. • Demonstrated ability to lead block PNR efforts, coordinate with RTL designers, physical design teams, and verification groups to meet aggressive tapeout schedules. • Familiarity with low-power design techniques and power- aware physical implementation.

Qualcomm India Private Limited is looking for a passionate STA and Synthesis Engineer to join their Engineering Group in Chennai. As an integral part of the cross-functional engineering teams, you will be engaged in all phases of design and development cycles, specifically focusing on Synthesis, Static Timing Analysis, and LEC of SoC/Cores. Your responsibilities will include full chip and block level timing closure, IO budgeting for blocks, logical equivalence checks between RTL to Netlist and Netlist to Netlist, as well as implementing low-power techniques such as clock gating, power gating, and MV designs. Additionally, you will be involved in ECO timing flow and should be proficient in scripting languages like TCL and Perl. The ideal candidate should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 2+ years of experience in Hardware Engineering. Alternatively, a Master's degree with 1+ year of relevant experience or a PhD in the aforementioned fields is also acceptable. Applicants with 1-5 years of experience are encouraged to apply. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact Qualcomm at disability-accommodations@qualcomm.com or refer to their toll-free number for assistance. Qualcomm also emphasizes the importance of compliance with company policies and procedures, including security measures for protecting confidential information. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities directly with Qualcomm. Agency submissions will be considered unsolicited, and Qualcomm does not accept unsolicited resumes or applications from agencies. For further details about this role, please reach out to Qualcomm Careers.,

You will be responsible for executing customer projects independently with minimum supervision, guiding team members technically in various fields of VLSI Frontend Backend or Analog design. As an individual contributor, you will take ownership of tasks/modules such as RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc., leading the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, delivering on-time quality work approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost accepted by UST Manager and Client. Additionally, you will be expected to write papers, file patents, and devise new design approaches. Your performance will be measured based on the quality of deliverables, timely delivery, reduction in cycle time and cost, number of papers published, number of patents filed, and number of trainings presented to the team. You will be expected to ensure zero bugs in the design/circuit design, deliver clean design/modules for ease of integration, meet functional specifications/design guidelines without deviation, and document tasks and work performed. Furthermore, you will be responsible for meeting project timelines, facilitating other team members" progress by delivering intermediate tasks on time, and seeking help and support in case of any delays. Your role will also involve active participation in team work, supporting team members as needed, anticipating when support may be required, and being able to explain project tasks and support delivery to junior team members. Your creativity and innovation will be showcased through tasks such as automating processes to save design cycle time, participating in technical discussions, training forums, white paper or patent filings, and contributing to technical discussions. Your skill set should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, Makefile, Spice, and familiarity with EDA Tools like Cadence, Synopsys, Mentor tool sets, and various simulators. You should have strong technical knowledge in IP Spec Architecture Design, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, Analog Layout, Synthesis, DFT, Floorplan, Clocks, P&R, STA, Extraction, Physical Verification, Soft/Hard/Mixed Signal IP Design, and Processor Hardening. Additionally, you should possess communication skills, analytical reasoning, problem-solving skills, and the ability to interact effectively with team members and clients. Your knowledge and experience should reflect leadership and execution of projects in areas such as RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and understanding of design flow and methodologies. Independent ownership of circuit blocks, clear communication, diligent documentation, and being a good team player are essential attributes for this role. Overall, your role will involve circuit design and verification of Analog modules in TSMC FinFet technologies, developing circuit architecture, optimizing designs, verifying functionality, performance, and power, as well as guiding layout engineers. Strong problem-solving skills, results orientation, attention to detail, and effective communication will be key to your success in this position.,

Cadence Design Systems is seeking a Lead Hardware Engineer for their DFT IP R&D team in Noida with 4-6 years of experience. As a member of the R&D staff, you will be working on Cadence's MODUS DFT software solution, a comprehensive product designed to achieve high coverage, reduced test time, and superior PPA. We are looking for candidates with expertise in various areas such as RTL design, DFT architecture, verification, power analysis, and optimization. This role involves developing cutting-edge DFT tools, designing and verifying RTL and test benches, and providing support to application and product engineers. You will be part of a team responsible for creating innovative technologies in the DFT space. Your responsibilities will include designing, developing, and supporting the MODUS software product. This position offers an opportunity to build a solid foundation in logic circuits and contribute to DFT IP tool development. The role involves enhancing usability and quality through feature enhancement and rigorous verification. You will also provide R&D support, problem analysis, debugging, and develop new features to optimize synthesis results for timing, area, and power. At Cadence, we value innovation and research. The successful candidate will receive mentoring and support to contribute to the EDA problem domain and enhance their problem-solving skills. The ideal candidate should be proficient in RTL design using Verilog and SystemVerilog, have knowledge of front-end EDA tools, SystemVerilog assertions, and advanced verification techniques. Familiarity with scripting languages like Perl or Python, DFT methodologies, and synthesis tools is desirable. Excellent communication skills are essential, along with a strong foundation in data structures and algorithms. Qualifications for this position include an M.Tech, M.E, B.Tech, or B.E. in EE/ECE/CS or equivalent, a good understanding of Digital Electronics, prior knowledge of Verilog/System Verilog, and EDA tools. Join us at Cadence to work on projects that truly matter and help us solve challenges that others can't.,

You should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, encompassing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial to have familiarity with ATPG, Low Value (LV), Built-in self-test (BIST), or Joint Test Action Group (JTAG) tool and flow. Ideally, you should also have experience with a programming language like Perl, along with expertise in Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC), DFT timing, and Static Timing Analysis (STA). Proficiency in performance design DFT techniques, understanding of the end-to-end flows in Design, Verification, DFT, and Partner Domains (PD), and the ability to scale DFT would be advantageous. As part of our dynamic team, you will be involved in developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in the innovation of products that are cherished by millions globally. Your skills will influence the next wave of hardware experiences, delivering exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team synergizes the best of Google AI, Software, and Hardware to craft profoundly beneficial experiences. We are dedicated to researching, designing, and advancing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to enhance people's lives through technology. Your responsibilities will include collaborating with a team dedicated to Design for Testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, Static Timing Analysis (STA) checks. You will be tasked with crafting Pattern delivery using Automatic Test Pattern Generation (ATPG), engaging in Silicon bring-up, working on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug, and delivering debug patterns while conducting Silicon data analysis.,

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what is possible. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. These systems encompass a wide range of components such as yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your work will contribute to the development of cutting-edge, world-class products that drive digital transformation and enable next-generation experiences. To qualify for this role, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with at least 3 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience in the relevant field will also be considered. As a Hardware Engineer at Qualcomm, your responsibilities will include front-end implementation of SERDES high-speed Interface PHY designs, RTL development and validation, collaboration with the functional verification team, development of timing constraints, UPF writing, DFT insertion, ATPG analysis, and support for SoC integration and chip level pre/post-silicon debug. The ideal candidate for this role should possess an MTech/BTech in EE/CS with 4 to 7 years of hardware engineering experience. You should have expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA, high-speed interface design, and industry-standard protocols like USB/PCIe/MIPI. Experience with post-silicon bring-up and debug is considered a plus, along with the ability to collaborate effectively with global teams and excellent communication skills. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com or Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking jobs directly at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through the site. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not entertain any fees related to such submissions. For further information about this role, you can contact Qualcomm Careers for assistance.,

Seeking an experienced physical design trainer to deliver VLSI training, design course content, lead interactive sessions, and provide hands-on guidance using industry-standard tools