1614 Sta Jobs - Page 5

Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/ Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementatio n (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 20+ years Hardware Engineering experience or related work experience. 17+ years experience with PNR flo...

We are seeking a Voice Specialist with 4+ years experience in speech synthesis and tuning. You will optimize prosody, tone, and clarity to create human-like, empathetic synthetic voices. Responsibilities: Fine-tune voice output metrics. Optimize intonation, flow, and contextual delivery. Collaborate with AI engineers on TTS integration. Monitor and evaluate synthesized voice quality. Bachelor s in Linguistics, Audio Engineering, or related field. Hands-on TTS/speech synthesis experience. Knowledge of phonetics and voice UX.

About The Role Your Role As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will collaborate closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process corners. In this role, you will: Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus) Collaborate with design and architecture teams to define timi...

Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from de...

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair eq...

Developing emulation testbenches to support necessary DV scenarios and firmware/software/hardware bring up Responsibilities Build emulation models from RTL and release/support those models Develop emulation tools such as debugger and monitor features Work closely with verification and software development teams Develop emulation and verification strategy Develop test framework and test cases Write documents such as verification specification and reports Coach younger colleagues Emulation and Prototyping technologies such as Palladium, Veloce, Zebu, HAPS, (these names are registered trade marks of their respective owners) Requirements Experience - minimum 15+ yrs and above with minimum of 5+ ...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Your Role Develop and maintainT4EA integrationsbetween Teamcenter and enterprise systems (e.g., SAP, Oracle, Polarion). Customize Teamcenter usingITK, SOA, BMIDE, AWC, andRich Client plugins. Implement and manageworkflow handlers,SOA services, andcustom extensions. Create and maintaintechnical documentationfor integrations and reports. Your Profile Strong experience withTeamcenter PLMandT4EA integration development. Proficiency inC, C++, Java, XML, XSLT, JavaScript, Angular, and TCL scripting. Hands-on experience withBMIDE,Active Workspace, andTeamcenter deploymentonAWS/Azure/GCP. Familiarity withMCAD/ECAD integration,ERP systems, anddata schemafor Part, BOM, and Change Management. Experienc...

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

Take on a new challenge and apply your electrical systems expertise in a cutting-edge field. Youll work alongside collaborative and innovative teammates. You'll be at the forefront of delivering power supply engineering solutions for traction projects such as metro, tramway, or mainline systems. Day-to-day, youll work closely with teams across the business (engineering, project management, construction, and testing teams), coordinate interfaces with various subsystems, and ensure the technical quality of designs and solutions. Youll specifically take care of providing electrical architectures, technical specifications, and validation of supplier equipment, but also follow-up on technical dra...

Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, youll contribute to developing next-generation networking chips. Responsibilities include: Being a member of design team who oversees fullchip SDCs and w...

Should have indepth experience in Floor-planning, CTS, Power routing, place and route, timing closure, DRC and LVS Should have worked on latest technology nodes (14nm or lesser) Should have worked on block level and top-level designs Good to have worked on designs without a customer flow. Strong problem-solving skills and communication skills. Ability to mentor and work closely with junior engineers Will be responsible for building a highly capable team of PD engineers at Ignitarium.

Requirements: 1) Cost Optimization and Efficiency Improvement Measure the actual achievement against each Logistics efficiency impacting Logistics cost viz Mode mix, STA, Source mix, Market mix etc. and compute the impact on the Total Landed Cos TLC by each Logistics variable Monitor the trends in the Logistics KPIs, identify the areas & scope of efficiency improvement for cost reduction and track the actual improvements against the identified scope Monitor Zonal cost parameters on real time basis and post analysis recommend corrective actions 2) Customer Service and Supply Chain Management Excellence Monitor Customer Satisfaction Level trends of Depots in Zone on regular basis and feedback ...

As a Physical Design Lead, you will be responsible for overseeing the RTL-to-GDSII flow for advanced technology nodes (7nm and below). Your role will include leading the physical implementation of SoC/IP, driving PPA goals, and ensuring successful tapeouts. You will be managing a team, collaborating with cross-functional groups, and taking ownership of block/top-level execution. Key Responsibilities: - Perform floorplanning, placement, clock tree synthesis (CTS), routing, and signoff - Conduct static timing analysis (STA), handle IR/EM, power & physical verification - Utilize EDA tools such as Innovus, PrimeTime, Calibre, etc. - Proficiency in scripting languages like TCL/Perl/Python, UPF, a...

You have been selected for a role as a Lead in SoC Physical Design at a dynamic company, 7Rays Semiconductor Private Ltd. With over 3 years of relevant experience, your expertise in SoC Physical design across multiple technology nodes, including 5nm for TSMC & Other foundries, will be highly valuable. Your responsibilities will include: - Demonstrating excellent hands-on P&R skills with expert knowledge in ICC/Innovus - Utilizing expert knowledge in all aspects of PD from Synthesis to GDSII - Demonstrating a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure - Experience at taping out multiple chips, especially...

We are hiring a Test Chip Design Engineer with hands-on experience in Test Vehicle development and Physical Design implementation. This role involves working on test chips used in IP validation, characterization, and silicon bring-up for one of the worlds leading semiconductor clients. If you are passionate about PD, STA, and PV, and want to work on cutting-edge process technologies, this opportunity is for you! --- Key Responsibilities: Execute Test Chip/Test Vehicle design for IP validation and characterization. Perform Physical Design (PD) activities floorplanning, placement, CTS, routing, and timing optimization. Conduct Static Timing Analysis (STA) and ensure timing closure across corne...

As an experienced digital design engineer at Terminus Circuits, your role will involve a deep understanding of protocols such as USB, PCIE, MIPI, JEDEC, I2C, and SPI. Your primary responsibility will be to design and verify RTL code for high-speed SerDes-related digital blocks. You must have excellent verbal and written communication skills to effectively collaborate with the team. Key Responsibilities: - Design and verify RTL code for high-speed SerDes-related digital blocks - Synthesize complex SoCs block/top level and write timing constraints - Conduct formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints - Perform post-layout STA closure and timing ECOs - Work on...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. Your role will encompass a wide range of tasks including working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. You will collaborate with cross-functional teams to meet performance requirements and develop innovative solutions. **Key Responsibilities:** - Lead a high performing team of engineers in the implementation domain for Display Sub-System - Manage multiple time-critical and complex projects effectively ...

As a Physical Design Engineer with full chip implementation expertise, including PnR, STA, and signoff flows, your role will involve working on advanced technology nodes and taking ownership from netlist to GDS-II. Key Responsibilities: - Execute full-chip PnR activities from Netlist to GDS-II - Hands-on experience in Floor-planning, Placement, CTS, Routing, Timing Closure (STA) - Perform signoff checks: FEV, VCLP, EMIR, PV - Work on Physical Synthesis through Sign-off GDS2 file generation - Manage signoff convergence, block-level timing signoff, ECO generation, and power signoff - Knowledge of high-performance and low-power implementation methods - Expertise in ICC2 / Fusion Compiler / Inno...

As an Implementation Engineer at Kinara, a Bay Area-based venture backed company, you will play a crucial role in leading and executing Synthesis and Static Timing Analysis (STA) for complex AI SoC designs with multi-mode and multi-power domain functionalities. Your responsibilities will include: - Conducting Synthesis and STA to ensure the quality and reliability of our products - Optimizing designs for low power and high performance with logically equivalent RTL - Implementing ECOs for functional and timing closure - Working with multi-clock, multi-power domain designs and multi-mode timing constraints - Inserting DFT and collaborating with different functional teams like RTL Design, DFT, ...

Role Overview: You are expected to execute any sized customer projects independently with minimum supervision and guide team members technically in any field of VLSI Frontend Backend or Analog design. As an Individual contributor, you will take ownership of any one or more tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc. and lead the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, ensuring on-time quality...

Responsibilities: Doing STD cells characterization work (max up to 40% of time) , Static timing analysis (60%) • Able to characterize basic STD Cells • Writing ARC for STD cell char (using primeLib , Silicon smart).lib QA check • Circuit understanding block wise , Full chip level • Static timing Analysis of DRAM block wise , top level analysis , cell level analysis • Writing constraints , analyzing the STA reports • Reporting violations to Design team , ownership for closure • Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions • Performing verification processes with modeling and simulation using industry standard simulators • Contribut...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The responsibility includes:-. -Independent planning and execution of Netlist-to-GDSII. -Good understanding of basics of static timing analysis. -Well versed with the Block level and SOC level timing closure (STA) methodologies, ECO generation and predictable convergence. -Should be able work in close collaboration with design, DFT and PNR team and resolve issues wrt constraints validation, verification, STA, Physical design, etc. -Should have good exposure to high frequency multi voltage design convergence. -Good understanding of clock networks. -Circuit level comprehension of timing critical paths in the...