1220 Sta Jobs - Page 5

General Summary: Are you interested in working with a world-class CPU design team? Are you interested in the application of formal methods to the verification of application processors? In contributing to the development of the next generation of formal methodologies in this space? Qualcomm's CPU team has some of the best CPU architects and engineers on the planet, developing the processors that will power the future. Come and join us on this exciting adventure. Sharpen your formal verification skills to their fullest on some of the complex designs ever attempted. Roles and Responsibilities: Work with design team to understand design intent and bring up verification plans and schedules with ...

General Summary: You will be implementing the industry's leading edge graphics processor, specific areas include 2D and 3D graphics, streaming processor, high speed IO interface and bus protocols. In this position, the designer will be responsible for architecture and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification. The successful candidate for this position will specify and design digital blocks in our Multimedia Graphics team that will be integrated into a broad range of devices. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering...

Job Title: RTL Design Engineer Work Mode: Hybrid Location: Noida Job Description • Work together with system architects and micro architects to define high level specifications that are implementable. • Contribute to RTL development including running tool flows like lint, CDC, Conformal low power and DFT checks • Work closely with functional verification teams on test-plan development and debug. • Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. • UPF writing, power aware equivalence checks and low power checks. • Collaborate with other functional teams including DFT, physical design and emulation teams to a...

STA and Timing closure of Infineon SoCs targeted for IoT and MCU markets. Job Description Responsible for leading STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets. Key contribution to timing sign-off methodology development for lower technology nodes (22nm and beyond). Ownership of constraints development for functional/test modes at pre and post layout stage. Opportunity to work on IO timing closure for critical interfaces like Serial Peripherals and External Memory Interfaces. Timing analysis and convergence of large hierarchical design across multiple modes and corners. Interact with RTL and DFT teams on timing feasibility and performance assessment. Work...

Career Area: Engineering Job Description: Your Work Shapes the World at Caterpillar Inc. When you join Caterpillar, youre joining a global team who cares not just about the work we do but also about each other. We are the makers, problem solvers, and future world builders who are creating stronger, more sustainable communities. We dont just talk about progress and innovation here we make it happen, with our customers, where we work and live. Together, we are building a better world, so we can all enjoy living in it. D e s i g n E n g i n e e r Machine Hydraulic integration Role D e f i n ition D e s i g n s , d e v e l o p s , b u i l d s , a n d im p l e m e n t s Hydraulics c o m p on ents...

Department FIL India Technology - WPFH - Testing About team Technology and engineering testing team is evolving at a fast pace to cater to strategic technology drivers and to meet end customer experience demands. Here experienced technologists drive this space with dedicated energy, passion, and inspiration and delivery quality solution with faster pace. About role The role would focus on services, functional, test automation and cover for key capability gaps and give this a shape of a programme with clear prioritised / agreed scope and agenda. The role will leverage/guide the existing automation experts to get this prioritised backlog delivered on time. The key outcomes shall be (but not li...

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Perform EMIR (Electromigration and IR drop...

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Timing models for AMS macros in multiple f...

We empower our people to stay resilient and relevant in a constantly changing world. Were looking for people who are always searching for creative ways to grow and learn. People who want to make a real impact, now and in the future. Does that sound like you? Then it seems like youd make a great addition to our vibrant international team. Youll make a difference by: Serving as the global technical authority and coach for Cabinets & Low Voltage Switchgears across regions. Driving the global commodity strategy in close collaboration with commercial partners, with strong emphasis on Cost & Value Engineering, Global Supplier Portfolio Management, Innovation, Quality, and Sustainability. Leading t...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

In this role, you will be leading all block/chip level physical design activities. This includes tasks such as generating floor plans, abstract views, RC extraction, PNR, STA, EM, IR DROP, DRCs, and schematic to layout verification. Collaboration with the design team to address design challenges will be a key aspect of this position. You will also be assisting team members in debugging tool/design related issues and constantly seeking opportunities to enhance the RTL2GDS flow to improve power, performance, and area (PPA). Troubleshooting various design issues and applying proactive interventions will be part of your responsibilities. Your main responsibility will be overseeing all aspects of...

We are looking for a highly experienced Clocking/Constraints/STA Lead to join our Physical Design team. In this critical leadership role, you will not only be responsible for your own technical expertise but also for guiding and mentoring a team of engineers to achieve exceptional timing closure for our IC designs. Lead the development and implementation of comprehensive clocking strategies for high-performance ICs. Define and manage timing constraints throughout the design flow, ensuring accurate and consistent timing analysis. Perform advanced Static Timing Analysis (STA) using industry-standard tools, identifying potential timing violations and bottlenecks. Develop and maintain robust clo...

At Cadence, we are seeking a talented individual to join our team and contribute to the world of technology. In this role, you will collaborate closely with various cross-functional teams across different locations to ensure alignment on project goals and deliverables. Your responsibilities will also include mentoring junior engineers, fostering innovation, and driving automation initiatives. The ideal candidate should hold a BE/B.Tech/M.E/M.Tech degree with at least 7 years of relevant work experience. A strong understanding of Design for Testability (DFT) concepts and excellent communication skills are essential. Additionally, hands-on experience with industry-standard EDA tools and logic ...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Description Required Solid RTL coding experience including Microarchitecture of design System Verilog and Verilog coding using provided coding styles. Understanding of SDC Understanding STA reports and how to ...

Role & responsibilities Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. • Own SDC constraint generation, validation, and refinement at top-level. • Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure. • Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimizations. • Conduct MMMC (Multi-Mode, Multi-Corner) timing analysis, including OCV, AOCV, and POCV variations. • Integrate timing reports from multiple blocks, perform hierarchical timing closure, and ensure sign-off compliance. • Work with DFT teams to analyze scan shift and at-speed test ...

Job Purpose To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement. Duties and Responsibilities 1.Resolving SFDC functions related issues2.Resolving BRE level issues3.Educating internal and field teams on issues due to training requirements4.Constant observations on the issues raised by the field team5.Raising regular IT request to resolve issues6.Constant communication between IT and Product teams to identify the changes7.Attending bi-weekly meetings with IT to find the bigger solution8.Find solutions to the repetitive problems and submit BRD9.Interacting with field teams to identif...

Job Purpose This position is open with Bajaj Finance ltd To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement Duties and Responsibilities Resolving SFDC functions related issues2 Resolving BRE level issues3 Educating internal and field teams on issues due to training requirements4 Constant observations on the issues raised by the field team5 Raising regular IT request to resolve issues6 Constant communication between IT and Product teams to identify the changes7 Attending bi-weekly meetings with IT to find the bigger solution8 Find solutions to the repetitive problems and submit BR...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

Requirements :Bachelors or Masters Degree with a strong VLSI BackgroundMinimum 3 years of experience in the area of Synthesis Synthesis Engineer: (3-10 Years)Key Responsibilities:Synthesis Environment setupValidating synthesis SDC qualityUtilize Synthesis tool variables and methodologies to extract the best area/power achievable for the process node Checking the synthesis DEF qualityAnalyze critical timing violation groups and congestion solve them by finetune floorplan or placement constraints Compare area/power with previous projects and check current project results DFT Insertion and debugging basic DFT issues Discuss directly with Design teams & Physical design teams to get the best synt...

RESPONSIBILITIES:Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checksEnsuring timing correlation between PnR STA and timely feedbacks to PD teamGenerating block level HS session and using Top context from SoC for Block-SoC Interface timing closure Generating timing ECO using Tweaker/PrimeClosure

Desired Profile : Expertise in C++ programming Expertise in Linux Kernel development Expertise in I/O execution / development experience on platforms / boards / SoCs Expertise working on Audio I/O (Azalia, Soundwire, I2S) Expertise in using GDC debugger and oscilloscope for analysing wave forms and debugging Strong knowledge on OS architecture Preferred resources with valid regional work permit