1614 Sta Jobs - Page 2

We are looking for a highly motivated and skilled Graduate Electrical Engineer with 2 to 4 years of experience to join our team at BuroHappold Engineering. The ideal candidate will have a strong foundation in electrical engineering principles and practices. Roles and Responsibility Design, develop, and test electrical systems, including power generation, transmission, and distribution. Collaborate with cross-functional teams to identify and prioritize project requirements. Develop and implement electrical safety protocols and procedures to ensure compliance with industry standards. Conduct site visits to inspect and troubleshoot electrical systems and equipment. Provide technical support and...

We are looking for a skilled Cloud Developer with 7 to 10 years of experience to join our team at Tessolve Semiconductor Pvt. Ltd. The ideal candidate will have a strong background in cloud computing and development, with excellent problem-solving skills. Roles and Responsibility Design, develop, and deploy scalable and secure cloud-based applications. Collaborate with cross-functional teams to identify and prioritize project requirements. Develop and maintain high-quality code using best practices and coding standards. Troubleshoot and resolve complex technical issues efficiently. Participate in code reviews and contribute to improving overall code quality. Stay updated with the latest tren...

We are looking for a skilled Full Stack Software Developer with 8 to 10 years of experience to join our team in Calypso Technology India Pvt. Ltd. The ideal candidate will have expertise in Java and React. Roles and Responsibility Design, develop, and test software applications using Java and React. Collaborate with cross-functional teams to identify and prioritize project requirements. Develop high-quality, scalable, and efficient code. Troubleshoot and resolve technical issues efficiently. Participate in code reviews and contribute to improving overall code quality. Stay updated with industry trends and emerging technologies. Job Requirements Strong proficiency in Java and React. Excellent...

We are looking for a highly skilled and experienced Senior Research Associate to join our team at SRF Limited. The ideal candidate will have 4 to 8 years of experience in research and development, with a strong background in this field. Roles and Responsibility Conduct experiments and collect data to support research projects. Analyze and interpret complex data sets to draw meaningful conclusions. Develop and implement new research methods and techniques. Collaborate with cross-functional teams to achieve project goals. Prepare and present research reports and findings to stakeholders. Stay updated with industry trends and developments. Job Requirements Strong understanding of research princ...

In this role, you will assist the Level 2 Coach in delivering safe, enjoyable, and challenging pre-planned sessions, while monitoring participants' attendance, progression, and achievements. You ll provide regular verbal and written feedback, help design and deliver workouts, and cover sessions for beginners when needed. Additionally, you ll stay updated with training, operate attendance and evaluation software, and be prepared for first aid and risk identification training in an aquatic environment. Teach & Coach the levels and age group Competent and Qualified for Deliver Safe, Enjoyable and Challenging Pre-Planned Sessions under the supervision of the Level 2 Coach To Monitor & keep parti...

Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively. Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation. Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for test. Identify opportunities to optimize clock skew and insertion delay across various corners and modes. Evaluate the clo...

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be designed and integrated Own the design and implementation of blocks to meet functional, timing, area and power requirements Guide and review verification for these blocks Design and implement logic functions that enable efficient test and debug Implement automation to increase design team efficiency PREFERRED EXPERIENCE: Strong front-end RTL engineering background Strong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineers Strong analytic and problem solving skills including the ability to analyze curren...

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- 1) Place and Route, CTS, Routability analysis with respect to congestion. 2) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) 3) Meeting RC requirements for manual/special signals 4) Good understanding of Calibre DRC/LVS/DFM, DFY, ERC and ESD latchup. 5) Responsible for all the integrity checks (chip-fin...

Your role and responsibilities Develop and maintain formal equivalence checking flows using Synopsys Formality. Collaborate with cross-functional teams to align verification methodology with design goals. Implement and support Formality ECO flows for incremental synthesis. Drive methodology improvements for SoC design verification. Coordinate with internal stakeholders and external vendors to deliver high-quality solutions. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelor€™s or Master€™s degree in Computer Science, Electronics Engineering, or VLSI Design. 5€“8 years of hands-on experience with Synopsys Formality o...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Verification Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :Full chip / Subsystem / Block level Physical verification for deep submicron technology 7nm and belowExpertise in LVS, ERC, PERC, DRC, Antenna, DFM, DensityDeep understanding of ESD analysisGood exposure to BUMP and RDL planningHands on experience with Innovus / Fusion compiler ...

As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- 1) Place and Route, CTS, Routability analysis with respect to congestion 2) we'll versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) 3) Meeting RC requirements for manual/special signals 4) Good understanding of Calibre DRC/LVS/DFM, DFY, ERC and ESD latchup 5) Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release, 6) Good scripting knowledge perl and TCL, familiar with Caliber, Innovus, 7) Understanding of VLSI fabrication process, 8) Implementing timing ECOs Implementing IR drop fixes, RC extraction, signal EM fixes, and Trans,...

Role & responsibilities STA engineer, for multinational company Preferred candidate profile • Block level Timing Constraints enablement & analysis ; • Clocking & Data flow understanding ; • Well versed in reviewing check_timing and Constraints QoR checks + Constraints Validation understanding ; • Able to interact with Implementation team counterparts for block timing closure ; • CTS building understanding along with Clock Tree spec review/closure ; • Timing ECOs & Final Timing last mile closure at block level ; • Scripting like TCL, Unix etc min 2.6 years of relevant experience is a must Immediate joiners highly preferred

Required skills: He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engrs. Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Timing...

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- 1) Place and Route, CTS, Routablity analysis with respect to congestion. 2) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) 3) Meeting RC requirements for manual/special signals 4) Good understanding of calibre DRC/LVS/DFM,DFY, ERC and ESD latchup. 5) Responsible for all the integrity checks (chip-finis...

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- 1) Place and Route, CTS, Routablity analysis with respect to congestion. 2) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) 3) Meeting RC requirements for manual/special signals 4) Good understanding of calibre DRC/LVS/DFM,DFY, ERC and ESD latchup. 5) Responsible for all the integrity checks (chip-finis...

This Position reports to: R&D Team Lead Your role and responsibilities In this role, you will have the opportunity to contribute to ABBs success with technology, software, product, and system development. Each day, you will identify and implement innovative solutions to relevant problems. You will also showcaseyour expertise by providing ideas and by being able to work both independently and as a part of a Research &Development (R&D) team. The work model for the role is: #LI- Onsite This role is contributing to the Motion Business for System Drive Division in Nelamangala - Bangalore India You will be mainly accountable for: Full technical ownership of the product. Should take ownership of th...

Mirafra Technologies Hiring STA Engineers: STA/Synthesis : Experience in handling complex data path oriented Multi-million gate synthesis. Working Knowledge on Physical synthesis using tools like Genus, Fusion Compile. Experience in debugging for multi-clock domains hierarchical/flat timing analysis Good working knowledge in multi-power domain synthesis and structural power checks using CLP. Hands-on experience in Formal verification along with strong debugging skills for resolving issues/aborts. Good Experience in synthesis timing closure and interactions with DFT and PD. Good knowledge on analyzing trade-offs and recipes for timing/area/power/congestion. Exposure in TCL scripting for usage...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Skills: VLE, Cadence Software, VLX, Calibre, DRC, LVS,. Layout Designer _ Hyderabad (5 to 8 Years. Description. Role and Responsibilities. Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work....

RTL Design Engineer Job Location: Bengaluru (BLR) and Hyderabad (HYD) Experience: 7 to 20 years About The Role : We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of ARM Micro Architecture to join our team. In this role, you will play a key role in the development of complex digital designs and contribute to the success of our cutting-edge projects. The ideal candidate will have a proven track record in RTL design and a deep understanding of ARM Micro Architecture. Key Responsibilities: Collaborate with cross-functional teams to define and develop RTL designs for advanced microprocessor-based projects. Design, implement, and verify digital logic bloc...

Physical Design Engineer Physical Design Engineer Experience 4-10 yrs Job Overview: Strong background of ASIC Physical DesignFloor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 5nm,7nm, 14nm, 10nm. Good knowledge of EDA tools from Synopsys, Cadence and Mentor Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS) Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida

SR. DFT ENGINEER SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and ...

RTL & Synthesis combined skills Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: 5-8 years of experience in RTL Design with exposure to synthesis OR 8+ years of experience in RTL Design Strong understanding of digital basics Proficiency in RTL coding (Verilog), IP design, and RTL integration Hands-on experience with LINT, CDC, and RDC Experience in writing UPFs and CLP/VCLP checks Familiarity with synthesis flow and validating design constraints Specific domain knowledge in ARM protocols, PCIe, Ethernet, RISC V, DDR, etc. Strong scripting knowledge Responsibilitie...

ASIC RTL Design Engineer Job Title: ASIC RTL Design Engineer Position Experience Level: 6 to 10 years Location: Bangalore About The Role : We are seeking a highly skilled and experienced ASIC RTL Design Engineer to join our team in Bangalore. The successful candidate will have 6 to 10 years of relevant experience and will play a crucial role in the design and integration of RTL components for complex ASIC projects. The candidate should possess a strong background in RTL UPF, SoC Design Integration, and multi-domain UPF methodologies. Additionally, a strong understanding of resolving VSI issues is required to excel in this role. Key Responsibilities: RTL UPF Experience: The ideal candidate sh...

SENIOR PHYSICAL DESIGN ENGINEER SENIOR PHYSICAL DESIGN ENGINEER SmartSoC is looking for smart and enterprising Physical Designer Engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. This role will involve Physical design at the block and chip level of complex designs in the latest technologies. Desired Skills and Experience- 3 – 10 years relevant experience Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background of Floor planning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing an...