402 Sta Jobs - Page 4

Job TitleAI/ML Engineer - Time Series Forecasting & Clustering LocationBangalore Experience2+ Years Job TypeFull-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting Build models to predict trends from time series data. Clustering Develop algorithms to group and analyze data segments. Data Insights Analyze data to enhance model performance. Team Collaboration Work with teams to integrate models into products. Stay Updated Apply the latest AI techniques to improve solutions. Qualifications: Education Bachelor s/Master s in Computer Science or related field. Experience Hands-on experience with time series forecasting and clustering. Skills Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and WellnessHealthcare policy covering your family and parents. FoodEnjoy scrumptious buffet lunch at the office every day. Professional DevelopmentLearn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and RecognitionsRecognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto Health & FamilyComprehensive benefits for you and your loved ones, ensuring well-being. Growth MindsetContinuous learning opportunities to stay ahead in your field. Dynamic & InclusiveVibrant culture fostering collaboration, creativity, and belonging. Career LadderInternal promotions and clear path for advancement. Recognition & RewardsCelebrate your achievements and contributions. Work-Life HarmonyFlexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Job Details: : Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure highquality integration of the IP block. Collaborates with postsilicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE. Qualifications: B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 7+ years of DFT experience Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Skill required: Network Services - Cisco Routing and Switching Operations Designation: Business Advisory Associate Qualifications: Any Graduation Years of Experience: 1 to 3 years What would you do? "Helps transform back office and network operations, reduce time to market and grow revenue, by improving customer experience and capex efficiency, and reducing cost-to-serveLooking for a candidate who has expertise in Networking and has good knowledge on fundamentals of NetworkA solution that validates the ability to install, configure, operate, and troubleshoot medium-size route and switched networks." What are we looking for? " Agility for quick learning Ability to work well in a team Process-orientation Written and verbal communication Network fundamentals Understanding all the networking devicesRouters, switches, etc. IP connectivity, access, addressing, and services Network security fundamentals Installation, Configuration, Operation, Administration, and Troubleshooting Fundamental IPv4 & IPv6 Business Networks Excellent Communication Problem Solving Skills Flexibility Teamwork Experience and working knowledge on OSI Layer 1 (Physical) and 2 (Datalink) troubleshooting (WAN point to point connection) Experience and working knowledge with IP, WAN, OSI layer, TCP/IP models, IPv4/v6 addressing, subnetting and Ethernet. Layer 1 to Layer 3 fault isolation and troubleshooting with telco providers and onsite technicians. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Familiarity with SDH, SONET, and Ethernet concepts Basic knowledge of cabling infrastructure such as patch panels, cross-connects and fiber types. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Experience working with global carriers in North America, LATAM, APAC, and/or EMEA Experience working in a multi-vendor DWDM optical environment Good English written/verbal communication and customer engagement skills Strong focus on providing an outstanding user experience Must be detail-oriented, with strong organizational skills Able to work independently and also in a team environment" Roles and Responsibilities: " In this role you are required to solve routine problems, largely through precedent and referral to general guidelines Your expected interactions are within your own team and direct supervisor You will be provided detailed to moderate level of instruction on daily work tasks and detailed instruction on new assignments The decisions that you make would impact your own work You will be an individual contributor as a part of a team, with a predetermined, focused scope of work Please note that this role may require you to work in rotational shifts Provide 24/7/365 monitoring of ticket queue, phones, and IRC channel Manage network events such as: Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updates Link Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity Provide 24/7/365 monitoring of ticket queue, phones, and IRC channel Manage network events such as: Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updates Link Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity and understanding of router show commands and how to interpret the output Manage client s optical network, manage alarms and faults in a multi-vendor environment, and Tracking of all work in ticketing system network interconnects with internal and external network operators Track and maintain a repository of RFOs and vendor improvements/actions and be able to represent client during external calls with 3rd party providers Manage troubleshooting, confirming fix and restoring traffic from network incidents reported by internal teams and third-party teams, engaging field resources and inventory teams as necessary. Track, coordinate and manage hardware recalls / minor card or part replacement, RMA part delivery, initiate production change requests and work with onsite techs for faulty card/part replacement Read/Parse vendor notifications and translate to Clients Production Change Request (PCR s) Look up affected circuits to include them in change request Escalate any emergency change requests for immediate review and scheduling Navigate ambiguity with unclear notifications from vendors - escalating as necessary or referring notification to other internal client teams" Qualification Any Graduation

Responsibilities: Build and guide a team of DFT engineers to deliver the architecture and the DFT deliveries towards SOC development. Engage with the RTL & physical design program management to plan and execute the DFT deliveries. Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise : At least 10+ years of experience in DFT implementation / methodology Strong understanding of digital design and test principles. Proficiency in DFT techniques, such as scan insertion, BIST, and Automatic Test Pattern Generation (ATPG), MBIST insertion Experience with EDA tools , Synopsys and Cadence &scripting languages (e.g., Python, TCL). Knowledge of IC design flows, verification tools, and fault models Ability to identify, analyze, and resolve testing challenges. Work effectively within multidisciplinary teams, communicating complex technical details clearly. Ensure thorough testing, comprehensive fault coverage, and alignment with industry standards. Technically lead/managed 10 - 15 DFT engineers to deliver DFT implementation on SOC Preferred technical and professional experience NA

We are looking for a talented and highly motivated research scientist to help advance our efforts in AI4Code, specifically focusing on testing and validation. In this role, you will work at the intersection of AI, software engineering, and testing, leveraging state-of-the-art techniques to enhance automated code analysis, test generation, and defect detection. You will collaborate with a multidisciplinary team to develop and deploy AI-driven solutions that improve software quality, reliability, and maintainability. Required education Doctorate Degree Preferred education Doctorate Degree Required technical and professional expertise Deep expertize in program analysis, formal verification. Proficiency in Python, Java, or other relevant programming languages. Familiarity with machine learning, NLP, or AI-driven software analysis. Experience with test frameworks, static analysis tools, or automated testing methodologies. Solid understanding of data structures and algorithms to enhance test generation and analysis. Passion for AI-driven innovation in software engineering Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

You Are: You are an experienced and initiative-taking individual with a strong technical background in STA at IP/block/full chip level implementation/methodology. You thrive in collaborative environments and possess a passion for creating innovative technology. Your expertise lies in working with advanced Finfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of our cutting-edge technology products. What Youll Be Doing: * Conceptualizing, designing, and productizing state-of-the-art RTL to GDS implementation for SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * Developing Digital BE activities includes synthesis, pre-layout STA, SDC constraints development, placement, CTS, routing and collaborating with the different functional teams to achieve optimal design solutions. * Post layout STA, timing & functional ECO development, timing signoff methodology at higher frequency IP designs closure. * Co-work with Place & Route team to resolve full chip/IP/block level layout integration issues to drive timing closure. * Coordinates with internal RTL IP owners on constraints related issues. * Creating new flows/methodologies and updating existing ones through collaboration with architects, Physical design and RTL design engineering teams. * Pre-layout and post-layout timing closure and timing model characterizations across various design corners to ensure reliability and aging requirements for Automotive & consumer products. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. * Optimizing performance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation in STA and signoff design methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You’ll Need: * BS/B.Tech or MS/M.Tech degree in Electrical Engineering with 5+ years of relevant industry experience. * Strong PD, pre& post layout STA and signoff experience, including SDC development, Mutli mode design development experience. *Experience in functional, test (shift, capture and at-speed ) constraints development experience and timing closure with MCMM is mandatory. * Experience in generating ECO for DRV cleaning and timing closure is mandatory. * Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/PT/PT-PX * Sound understanding of Physical design, STA and signoff concepts. *Proven track record of successful timing closure & tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm,3nm,2nm etc...) *Good understanding of OCV, POCV, derates, crosstalk and design margins. * Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providing physical design and signoff solutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals.

TECHNICAL LEAD – DFT SmartSoC is looking for a smart and enterprising leader with expert knowledge in DFT to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking. You will be responsible for leading and managing a team, client communication, and project execution. Job Responsibilities- Lead an internal DFT team, executing projects for an offshore client Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 7+ years of experience in DFT, mainly Scan Architecture, ATPG & MBIST Experience in planning scan chains, running scan insertion flow Experience in latest Cadence tool set Genus & Modus Experience in ATPG for Stuck@, TFT, IDDQ & Path delay faults with tough coverage targets Experience in MBIST architecture, generation and implementation Experience in AECQ100 requirement standard is a big plus Experience in working with a multi-site team is a big plus Experience in working on critical time-bound projects is a big plus Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Bangalore,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. Applied Materials is the leader in materials engineering solutions to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. Our innovations make possible„¢ the technology shaping the future. To achieve this, we employ some of the best, brightest, and most talented people in the world who work together as part of a winning team. Key Responsibilities Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in future technology nodes Ability to implement solutions and troubleshoot complex problems with limited or no supervision in area of expertise Creative thinking and ability to look ahead and anticipating future technology innovations/issues Ability to collaborate with internal stakeholders, customers and vendors Collaborate/participate in discussions to solve interdisciplinary technical issues in a cross-functional team environment Mandatory - PDK, DRC, LVS, Python, Physical Design Functional Knowledge Demonstrates depth and/or breadth of expertise in own specialized discipline or field Business Expertise Interprets internal/external business challenges and recommends best practices to improve products, processes or services Leadership May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Problem Solving Leads others to solve complex problems; uses sophisticated analytical thought to exercise judgment and identify innovative solutions Impact Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies interpersonal Skills Communicates difficult concepts and negotiates with others to adopt a different point of view Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s microprocessor chip design team. As a member of DFT team, you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in processor flow and post silicon validation

Full time with century old top Japanese MNC JOB SUMMARY ( Full time with Super Top Japanese MNC) JDs follow for following roles, Principal Engineer VLSI Semiconductor Chip Design Analog Principal Engineer VLSI Semiconductor Chip Design Backend Principal Engineer VLSI Semiconductor Chip Design Frontend ------------------------------------------------------------------------------------------------------------------------------------------ Job Title : Principal Engineer Chip Design Analog Job Title: Principal Engineer - Analog IP/IC Job Overview: As an Principal Engineer - Analog IP/IC specializing in Semiconductor Chip Design, you will lead and coordinate the execution of analog and mixed-signal integrated circuit development projects. This role requires a strong technical background in analog design, verification, and physical implementation, coupled with exceptional project management skills. You will oversee teams engaged in designing high- performance analog circuits, ensuring precision and reliability in semiconductor designs. Key Responsibilities: Design analog/mixed-signal blocks: ADC/DAC, PLL, LDO/DCDC, IO, Motor & Gate Drivers . Run MATLAB modeling , circuit simulations , and post-layout analysis (LPE, Monte Carlo). Develop and manage verification plans , mixed-signal simulation , and behavioral models . Guide custom layout and ensure DRC/LVS/ESD/DFM compliance. Collaborate with digital, verification, layout, and test teams. Use industry-standard EDA tools (e.g., Custom Compiler). Product Support Required Skills & Experience Required Skills & Experience Min 8+ years of experience in custom analog/mixed signal design Strong in variation-aware design, verification planning, and cross-functional teamwork. Layout Parasitic Extraction (LPE), Custom IC Design, EDA Tools for Analog Design Strong design and debugging skills. Experience in Product Support for both Pre and Post Production Stages, Support for RMA teams. Preferred Skills and Experience Min 1+ years of Project Management (Waterfall and Agile Hybrid Methodology). Continuous Improvement. Qualifications: Masters in VLSI design from reputed universities like IIT/NIT with a background in Bachelors in Electronics and Communication, or a related field ------------------------------------------------------------------------------------------------------------------------------------------------------ Job Title : Principal Engineer Chip Design Back End Job Overview: : As a Backend (Physical Design) Principal Engineer specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the back-end stages of integrated circuit development. This role requires a strong technical background in physical design, a deep understanding of semiconductor processes, and exceptional project management skills. You will oversee teams engaged in physical design, synthesis, DFT, place and route, power integrity, and other back-end aspects to ensure the successful realization of semiconductor designs. Additionally, you will oversee product support activities for both Pre-production and Post-production stages, ensuring the successful initiation, development, and sustainment of semiconductor designs. Key Responsibilities: Technical Leadership - Own synthesis, SDC constraint development, and formal verification. - Drive place & route (P&R) including floorplanning, CTS, and timing closure. - Optimize for power, performance, and area (PPA); manage power distribution and multi-voltage design. - Lead STA across corners/modes and support technology node migration. - Integrate and verify SCAN/MBIST, define test specifications, and debug test coverage issues. - Perform DFM, DRC, and ESD checks to ensure manufacturability. - Collaborate with cross-functional teams (Frontend, Analog. - Document design flow, participate in design reviews, and mentor junior team members. - Product Support and RMA support Required Skills & Experience - Min 8+ years of strong experience in backend flows for MCU or low-power SoC designs . - Ability to lead the DFT teams, Physical and formal Verification Teams. - Exposure to frontend and Analog processes. - Ability to collaborate effectively with frontend and analog teams - Experience in Product Support for both Pre and Post Production Stages, Support for RMA teams. Preferred Skills and Experience - Min 1+ years of Project Management (Waterfall and Agile Hybrid Methodology). - Continuous Improvement. - Knowledge of industry standards and best practices in semiconductor front-end design. Qualifications: Masters in VLSI design from reputed universities like IIT/NIT with a background in Bachelors in Electronics and Communication, or a related field. ---------------------------------------------------------------------------------------------------------------------------------------------- Job Title : Principal Engineer – Chip Design Front End Job Overview: As a Frontend Principal Engineer specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the front-end stages of integrated circuit development. This role requires a strong technical background in digital design, verification, and project management skills. Additionally, you will oversee product support activities for both the Pre-production and Post-production stages, ensuring the successful initiation, development, and sustainment of semiconductor designs. Key Responsibilities: Technical Leadership and Architecture Design Architecture from scratch for new products and understand the specifications of the derivative products. RTL Design and Coding, Code Quality Management : Creating RTL Design and Coding.. Ensure highest quality by applying suitable coding standards and other techniques. Design Verification : Ensuring the correctness and functionality of the design through rigorous verification processes. This includes creating test benches, running simulations, and debugging the design. Collaboration : Working closely with other teams, such as physical design, analog IP/IC, software, and system engineering teams, to ensure seamless integration and functionality of the final product. Mentorship and Leadership : Leading and mentoring junior engineers, providing guidance on best practices, and ensuring the team adheres to project timelines and quality standards. EDA Tools Proficiency : Utilizing EDA tools for design, simulation, and verification tasks. Documentation : Maintaining detailed documentation of the design process, including specifications, design decisions, and verification results Product Support : Pre and Post Production Stages, Support for RMA Required Skills & Experience - Min 8+ years of experience in System Architecture for ARM based MCU product development - Min 8+ years of experience in RTL Design, Coding and RTL Integration, - Strong design and debugging skills. - Experience in handling Verification Teams. Verification environment Development , Static and Dynamic Verification, Test Management. (UPF, GLN, Test Mode) - Experience with industry-standard EDA tools for LINT, CDC, SDC validation, and power analysis preferably Synopsis EDA. - Exposure to Backend and Analog processes. - Ability to collaborate effectively with backend teams (PD, DFT, and STA) to achieve timing and power closure. - Experience in Product Support for both Pre and Post Production Stages, Support for RMA teams. Preferred Skills and Experience - Min 1+ years of Project Management (Waterfall and Agile – Hybrid Methodology). - Continuous Improvement. - Knowledge of industry standards and best practices in semiconductor front-end design. Qualifications: Masters in VLSI design from reputed universities like IIT/NIT with a background in Bachelors in Electronics and Communication, or a related field

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Bangalore Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Bangalore Work Locations: Lulu Mall (Rajajinagar) Phoenix Marketcity (Whitefield) Shift Timing: 12:00 PM 5:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 3,000 3,500 Work 4 5 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend work Opportunity to work with a popular restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

Role & responsibilities Physical Design Engineer (PD/STA/Synthesis) Must-Haves: •Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA •Flow Experience: •Floorplanning •Power planning •Placement •Clock Tree Synthesis (CTS) •Routing •Physical Verification (DRC/LVS) •Timing Closure •Knowledge of: •Low-power design (UPF/CPF) •ECOs •IR Drop, EM Analysis •STA constraints and timing analysis Nice-to-Haves: •Experience with block-level and/or full-chip PD •Familiarity with scripting (Tcl, Perl, Python)

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Chennai Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Chennai Work Locations: T. Nagar Nungambakkam Vadapalani Velachery Thuraipakkam Marina Mall (Egattur) Shift Timing: 11:00 AM 8:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend shifts Work experience with a leading restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Kolkata Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Kolkata Work Locations: Salt Lake (City Centre Mall) Park Street (Opposite The Park Hotel) New Town (Axis Mall) Howrah (Avani Riverside Mall) Gariahat (Near Mukti World Mall) Shift Timing: 12:00 PM 9:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Assist kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend opportunity Experience working with a reputed restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Mumbai Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Mumbai Work Locations: Andheri West (Infinity Mall) Lower Parel (High Street Phoenix Mall) Thane (Viviana Mall) Malad (Inorbit Mall) Vashi (Raghuleela Mall) Shift Timing: 12:00 PM 9:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Assist kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend work Work experience with a leading restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Hyderabad Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Hyderabad Work Locations: Banjara Hills (Near City Center Mall) Gachibowli (SLN Terminus) Hitech City (Opposite Cyber Towers) Kukatpally (Forum Sujana Mall) Begumpet (Near Lifestyle Building) Shift Timing: 12:00 PM 9:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Assist kitchen and service staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend work Work experience with a reputed restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

Primary & Mandatory Skill: Python, Docker/Kubernetes Level: SA Client Round (Yes/ No): No Location Constraint if any : No Shift timing: 2-11pm JD: Good hands in Python scripting Experience in Docker & Kubernetes

Primary/ Mandatory skills : Extensive experience in “Chef IT Automation” Secondary skills : Good knowledge and experience in DevOps Level: SA RR : Maintain a consistent terraform script when compared to existing cloud resources Chef version update: version 14 to version 18 Crowdstrike, Qualys and Splunk integration for Ecommerce workloads Packer AMI creation for Windows Core and CentOS Stream 9 Terraform version update Collaborate with DB team for “CentOS version + DB version” update project Test every change made. Work with DevOps, SRE and development teams for testing. Document and publish the changes, and projects undertaken. Client Round (Yes/ No): Yes Location Constraint if any : No Constraints Shift timing: IST 1330Hrs – 2330Hrs

Key Responsibilities: Lead end-to-end physical design flow for complex blocks or full-chip designs. Drive floorplanning, power planning, placement, CTS, routing, and physical verification (DRC, LVS). Optimize timing, power, and area to meet design specifications. Perform hierarchical/flat implementation based on project needs. Work closely with RTL, DFT, STA, and packaging teams. Manage and mentor a team of physical design engineers. Interact with EDA vendors to improve tool flows and resolve tool-related issues. Contribute to methodology improvements and script automation for design efficiency. Required Skills and Qualifications: B.Tech/M.Tech in Electronics/Electrical Engineering or related field. 8+ years of hands-on experience in physical design with deep expertise in block and full-chip implementation. Strong knowledge of EDA tools: Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime, RedHawk/Totem, etc. Solid understanding of STA, IR/EM analysis, congestion analysis, and ECO implementation. Experience on advanced nodes (7nm/5nm/3nm) is highly desirable. Prior leadership or team management experience. Strong debugging, scripting (Tcl, Perl, Python), and communication skills.

Video Editing Intern Jaipur (In-office) - Digi Spheres Video Editing Intern Jaipur (In-office) Job Summary: We re seeking a creative and technically skilled Video Editing Intern to bring our content to life. You ll be responsible for editing short-form and long-form content for various platforms. Key Responsibilities: Edit videos, reels, and motion graphics for client campaigns Add music, text, transitions, and other visual effects Optimize content for Instagram, YouTube, and other platforms Collaborate with content creators and strategists for ideation Requirements: Proficiency in Premiere Pro, Final Cut Pro, or CapCut Strong sense of pace, timing, and narrative flow

Role & responsibilities DFT Engineer Must-Have: •Tools: Synopsys DFT Compiler, Tessent, Mentor TestKompress, Tetramax, Fastscan •Techniques: •Scan Insertion (ATPG) •Boundary Scan (JTAG) •MBIST, LBIST •Compression techniques •Stuck-at, Transition fault models •Simulation and validation of test vectors •DFT signoff and coverage reports •STA constraint generation for test modes Nice-to-Haves: •Tapeout experience •Knowledge of low-power test techniques •Integration of DFT at SoC level Common Green Flags Across Roles: •Product or IP ownership •Clear mention of project responsibilities (not just team contribution) •Mention of tapeouts or silicon-proven designs •Stable employment history (avoiding frequent jumps unless justified) •Notice period 90 days •Clarity in resume: tools, technology nodes, project domains

Here's the information about the PrimeTime role, formatted for clarity and impact: Driving increased usage of the Synopsys PrimeTime tool through both pre-sale and post-sale activities. Conducting competitive benchmarks and evaluations to demonstrate the superiority of our products. Articulating technical advantages to customer design teams and management. Providing customer training and tapeout support to ensure successful product implementation. Collaborating with users, R&D, marketing, and sales teams to enhance product features and usability. Engaging in advanced collaboration initiatives to drive continuous product improvements. The Impact You Will Have Increasing the adoption and integration of PrimeTime, leading to higher customer satisfaction and retention. Enhancing customer design processes through expert guidance and support. Contributing to the development of superior product features based on customer feedback and industry trends. Strengthening Synopsys market position through effective pre-sale evaluations and demonstrations. Facilitating successful tapeouts and design completions for customers using PrimeTime. Driving innovation within Synopsys by collaborating with multiple teams and stakeholders. What You'll Need BSEE with 5+ years of experience or MSEE with 3+ years of experience in related fields. Domain knowledge in Static Timing Analysis (STA) and expertise in timing closure and ECO flows . Experience with Synopsys STA tools , particularly PrimeTime. Understanding of timing corners, modes, process variations, and signal integrity issues. Strong knowledge of TCL scripting and familiarity with synthesis, physical design, and extraction methodologies. Who You Are A proactive and detail-oriented professional with strong technical acumen. An effective communicator with excellent verbal and written communication skills. A collaborative team player who thrives in customer-facing roles. An innovative thinker who is always looking for ways to improve processes and products. A dedicated individual with a strong sense of ownership and responsibility.

Desired Skills and Experience: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl or Python scripting skills. Prior experience with logic synthesis tools is required. Prior experience using or supporting SDC tools would be a significant plus. Prior experience with RTL simulation, SVA would be a plus. Prior experience supporting front-end EDA tools would be a plus. Sound communication skills, verbal and written. Ability to produce product requirement documents. BS EE/CE. 4 years experience with STA/Synthesis.