1220 Sta Jobs - Page 6

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills:

Education : BTech in ECE/EEE or MTech VLSI No. of positions : 5 Desired Skills: Minimum 3+ year of experience Should have block/SOC level netlist-gds2 experience. Expertise in Floor planning, Power planning, CTS. Should be capable of handling block-level timing closure. Good scripting skills (TCL/Perl/Shell). Experience on low power implementation techniques is preferred. Synopsys/Cadence tool experience is preferred. Should be a team player and perform lead role where ever required. Good communication analytical skills.

Lead a team of 5-10 resources Understand the design specification , PowerOn Specification Understand boot firmware and reset flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and in...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

As a Senior Digital IC Design Engineer at onsemi, you will be a part of the Digital Compute Team, contributing to the development of embedded MCU/DSP systems. Your responsibilities will include architecting, specifying, implementing, simulating, and benchmarking MCU and DSP systems, as well as hardware accelerators. You will collaborate with product integration teams, provide consultation during system integration, and participate in verification and FPGA prototyping activities. Additionally, you will lead project activities, coordinate SDK development with the software team, and contribute to design methodology and flow improvements. To excel in this role, you should possess a minimum BS/MS...

ofAbout the Job 3 to 8 years of relevant experience Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and pref...

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibiliti...

Experience : 4-10 Yrs Location : Blre 4-10 years experience with Bachelors degree in Electronics Engineering or equivalent Knowledgeable in all aspects of deep submicron ASIC design flow. Knowledgeable in Static Timing Analysis, Power Analysis and Innovus. Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages. Experience in developing PD metrics dashboard scripts for QOR tracking is a plus Experience in modifying STA constraints to check timing closure feasibility Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targe...

Wipro Limited is a leading technology services and consulting company dedicated to creating innovative solutions that cater to the most complex digital transformation requirements of clients. With a global presence spanning 65 countries and a workforce of over 230,000 employees and business partners, Wipro is committed to helping customers, colleagues, and communities thrive in an ever-evolving world. For more information, please visit www.wipro.com. As a Physical Design Lead, you will be based in Bangalore, Hyderabad, or Pune with a minimum of 8 years of experience. Your responsibilities will include handling Netlist2GDSII Implementation tasks such as Floor planning, Placement, CTS, Routing...

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group, specifically in the Hardware Engineering area. As a Hardware Engineer at Qualcomm, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other systems to contribute to the development of cutting-edge products. You will collaborate with cross-functional teams to find solutions and meet performance requirements. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 4 years of experience in Hardware Engineering, or a ...

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements effectively. Minim...

Qualcomm India Private Limited is looking for an experienced ASIC Design Engineer to join their Engineering Group, Hardware Engineering division. As an ideal candidate, you should hold an MTech/BTech in EE/CS with a minimum of 7 years of experience in ASIC design. Your responsibilities will include micro-architecture development, RTL design, front-end flows, synthesis, DFT, FV, and STA. A good understanding of DDR families and generations, as well as protocols like AHB/AXI/ACE/CHI, will be advantageous. Experience with post-silicon bring-up and debug is a plus. You should be able to collaborate effectively with global teams and possess strong communication skills. Hands-on experience in Mult...

Job Description Key Responsibilities: Timing Analysis & Closur e Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. Achieve timing closure by resolving violations and optimizing paths. Constraint Development Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths). Integrate constraints from multiple IPs for hierarchical STA. Tool Usage & Flow Integration Use STA tools like Synopsys PrimeTime, Cadence Tempus , or equivalent. Integrate STA into the overall design flow and automate processes for efficiency. Job Description: Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, an...

Skills: Billing Search for relevant government/private tenders (GeM, eProcurement sites), Download tender documents and study scope, terms, and eligibility, Coordinate with technical and sales teams to prepare documentation, Prepare and submit tender forms, EMDs, and supporting documents, Track tender deadlines, corrigendums, and submission status, Maintain tender submission records and files (both soft and hard copy),

Job Responsibilities : Maintain smooth plant operation with adherence to SOP'S and SOC's Check process parameters as per schedule and monitor chemicals and utility consumption Monitor trends of critical parameters to identity impending abnormalities and notify shift in-charge (shift superintendent) for corrective actions Coordinate system shutdown and start up through panel operation and communication to field Follow guidelines received from shift superintendent (shift in-charge) through Shift Team Meetings / OMPRO instructions for enhancement of plant operations Continuously monitor the panel for any significant changes in operating parameters, alarms etc and take corrective action whenever...

Role: Design Analysis Engineer (FPGA/Vivado) [M.Tech Mandatory] What they do: Analyze design issues in Vivado implementation flow. Apply and debug timing constraints to ensure design closure. Propose/design corrections to fix issues. Use scripting (Shell/Python/TCL) to automate and improve analysis. (RTL/Verilog knowledge is optional, not mandatory.) Mandatory Skills: Strong in Timing Constraints (STA concepts) Hands-on with Vivado tool flow Shell/Python/TCL scripting for automation Good to have: Quartus exposure Basic RTL/Verilog understanding In short: This is not an RTL coding role. Its a timing + Vivado design analysis role with scripting. Feel free to share the resume if you feel its a ...

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills:

Education : BTech in ECE/EEE or MTech VLSI No. of positions : 5 Desired Skills: Minimum 3+ year of experience Should have block/SOC level netlist-gds2 experience. Expertise in Floor planning, Power planning, CTS. Should be capable of handling block-level timing closure. Good scripting skills (TCL/Perl/Shell). Experience on low power implementation techniques is preferred. Synopsys/Cadence tool experience is preferred. Should be a team player and perform lead role where ever required. Good communication analytical skills.

You will be part of a highly skilled and challenging high-speed parallel PHY design team, working on interfaces such as DDR, LPDDR, etc. Your responsibilities will include designing and developing high-speed interface PHY and its sub-blocks, such as high-speed data paths, analog calibration, training, IP initialization, low power control, test, loopback, etc. You will be accountable for various aspects of design and verification from specification to silicon, as well as interface design for the controller and SoC. Your role will also involve active participation in problem-solving and implementing opportunities for improvement. Additionally, you will mentor and coach other design team member...

Job Description for RTL We are hiring a SoC Integration Engineer with strong expertise in RTL coding and SoC integration flows. The ideal candidate should have hands-on experience with SpyGlass Lint, CDC, DC Synthesis, and VCLSP, along with scripting knowledge. Key Responsibilities: Integrate IP blocks into SoC at RTL level Perform RTL coding and micro-architecture design (Verilog/VHDL) Run and debug SpyGlass Lint, CDC, and DC Synthesis flows Conduct STA and design rule checks Develop automation scripts (Perl, Python, Shell, Tcl) Collaborate with verification and physical design teams Work on VCLSP and SoC-level integration flows Primary Skills: RTL Design: Verilog, VHDL, Micro-architecture ...

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in...

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal me...

RTL Design Engineer 4+yrs experience Location: Hyderabad_onsite Malayasia Advanced RTL Design and DFT trainee, looking forward to build a career in the VLSI domain. To work with full determination and dedication, to achieve organization as well as personal goals. Skills : Verilog, Design for Testability (DFT), RTL Coding, STA, System Verilog, C, FPGA design Hands-on experience : Router 1x3 - Design using Verilog, RISCV32I Processor- RTL Design and DFT

7-15 years of experience in static timing analysis for digital IC design. Strong understanding of digital design concepts, including flip-flops, latches, combinational logic, and clocking methodologies. Proficiency in using STA tools like Synopsys PrimeTime, Cadence Tempus, or similar tools. Experience with timing optimization techniques and methodologies. Knowledge of various design flows, including RTL design, synthesis, and physical design. Familiarity with scripting languages such as Perl, Python, or Tcl for automation of STA tasks. Strong analytical and problem-solving skills with attention to detail. Excellent communication skills to collaborate effectively with cross-functional teams.