1614 Sta Jobs - Page 6

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Description Required Solid RTL coding experience including Microarchitecture of design System Verilog and Verilog coding using provided coding styles. Understanding of SDC Understanding STA reports and how to ...

You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. As a DFT engineer direct responsibilities of the role, but not limited to, working on various aspects of PCORE DFT including Spyglass DFT, RTL implementation, Verification, Scan, and ATPG. The candidate must be able to drive the DFT implementation for various features incl Scan, MBIST, TAP, etc. Previous experience working with manufacturing engineering, pattern delivery, and post-silicon support is a definite plus. Qualifications: Candidate must possess a Master's degree in Electronics or Computer Engineering with at least 7 or more years of experience or a bachelor's de...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

Job Title FPGA RTL Design Engineer Wireless ORAN Domain Location BLR client site Experience 10 to 12 years 2 Engineers 6 to 10 years 2 Engineers Total number of positions 4 About the Role RTL Design Engineers with deep expertise in telecom domain with exposure in ORAN. You will work closely with the customer to develop cutting edge ORAN equipment to cater to control plane and data plane implementations. Key Responsibilities Work with system architect to understand the requirements and design efficient RTL implementations targeting FPGAs. Translate MATLAB models to RTL for hardware realization MATLAB Simulink based modelling simulation and conversion to RTL Develop RTL architecture and microa...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Engineer Grade: T3 Experience: 4-6 Years Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications...

Altera is seeking highly skilled Senior/Lead FPGA Silicon Design Engineer to ensure the excellence of next-generation Ethernet/Transceiver/Crypto for top-tier FPGAs. This role offers opportunity to make a significant impact at a tech-driven company that provides leading programmable solutions, easily deployable in applications ranging from embedded, industrial, & cloud to edge, unlocking limitless possibilities Responsibilities: Develop Micro-architecture and Design implementation for Ethernet/Transceiver/Crypto IPs and subsystems. Work closely with the Architects to come up with an optimal design, RTL code development, involvement in pre-silicon and post-silicon debug, and own all the front...

Semiconductor STA Design Engineer Desired experience 3-10 Years TSMC Certification Yes/No Role You will be responsible for analyzing digital and analog circuits used in the development of memory products. Responsibilities • Doing STD cells characterization work (max up to 40% of time) , Static timing analysis (60%) • Writing constraints , analyzing the STA reports • Performing verification processes with modeling and simulation using industry standard simulators • Able to characterize basic STD Cells Writing ARC for STD cell char (using primeLib , Silicon smart) QA check Circuit understanding block wise , Full chip level Static timing Analysis of DRAM block wise , top level analysis , cell l...

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong plann...

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent comm...

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. PD JD: Thorough knowledge of the ASIC designs Place and Route flow and methodology. Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level...

Experience in ASIC/SoC Physical Design & STA implementation (Synthesis to GDSII). EDA tools - Synopsys: Design Compiler, ICC2, PrimeTime. Cadence: Innovus, Tempus, TCL, Perl, Python, Shell STA concepts — setup/hold analysis, OCV/AOCV, SI, & Crosstalk

Key Responsibilities: Lead the architecture, design, and integration of SoC-wide clocking networks including clock generation (PLLs, DLLs), distribution, gating, and domain crossing strategies. Define and optimize power-performance-area (PPA) trade-offs for complex clocking and circuit topologies. Collaborate cross-functionally with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP. Own the technical roadmap and methodology improvements for clocking, timing closure, and custom circuits. Mentor and technically guide a team of junior and senior designers. Review and approve specifications, schematics, simulations, and post-layout signoff for hig...

Roles and Responsibilities: Perform RTL-to-GDSII implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure. Work on P&R flows using tools such as Cadence Innovus / Synopsys ICC2 . Handle timing analysis and sign-off using PrimeTime / Tempus . Perform power planning, IR-drop, and EM analysis to meet reliability targets. Execute DFM closure DRC/LVS/ANT checks using Calibre . Implement ECOs for timing, functionality, and metal fixes. Work closely with front-end, verification, and DFT teams to ensure full-chip integration and timing convergence. Optimize Power, Performance, and Area (PPA) for block- and top-level designs. Contribute to flow automa...

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical ...

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8-10 years of industry experience in physical design methodology. Good knowledge and hands-on experience in physical design methodology, which includes logic synthesis, placement, clock tree synthesis, routing. Should be knowledgeable in phy...

Job Details: Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verif...

Job Details: If you are a senior leader with expertise in Design for Test and are passionate about defining the future of Client and Hyperscaler designs and SoC's, Intel has opportunities for you.The Central Engineering group is responsible for delivering industry-leading Custom Silicon Solutions for Intel Customers in the Client and Hyperscaler Domains. The DFT Director's responsibilities include (but are not limited to): Lead the product DFT Architecture for the Intel Custom Silicon Business Drive DFT technical readiness (TR) and define DFT strategy to meet the Intel Manufacturing requirements Work with the team to define DFT quality control/process for SoC execution predictability and hig...

Job Description: We are looking for a Lead STA (Static Timing Analysis) Engineer to join our semiconductor design team. The ideal candidate will have extensive experience in ASIC/SoC timing analysis, closure, and signoff , along with deep knowledge of industry-standard tools like PrimeTime or Tempus . You will be responsible for driving timing closure , ensuring robust design constraints, and collaborating with Physical Design, Synthesis, and Signoff teams to deliver high-performance silicon. Roles and Responsibilities: Perform Static Timing Analysis (STA) across multiple corners and modes (MMMC). Debug and resolve setup, hold, recovery, and removal violations. Own and maintain timing constr...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...