1220 Sta Jobs - Page 7

Synopsys (India) Private Limited is looking for ASIC Digital Design, Staff Engineer to join our dynamic team and embark on a rewarding career journey Lead and execute complex engineering projects. Collaborate with cross-functional teams to develop innovative solutions. Mentor and guide junior engineers. Ensure compliance with industry standards and regulations. Conduct technical reviews and assessments. Identify and mitigate project risks. Maintain up-to-date technical documentation.

Synthesis and Timing engineer to participate in the development of large SOCs with multiple physical blocks and 300+ clock domains. He/She must be high energy candidate with strong written and verbal communication skills, technically strong to find solutions and help the team both inside and outside the organization. REQUIRED SKILLS: RTL Design Quality checks, mainly Lint Automation using Python and TCL 5years+ experience, so not an NCG KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process...

Lead the architecture and RTL design of complex digital blocks and subsystems for ASICs or SoCs Develop RTL using Verilog/SystemVerilog to meet functional and performance specifications Review micro-architecture and provide design solutions optimized for power, performance, and area Work closely with the verification team to ensure thorough test coverage and efficient debugging Collaborate with synthesis, STA, and physical design teams for design closure

This is what you are responsible for Develop verification environments for modules, subsystems, top level and FPGA Build models, checkers and random test frameworks using SystemVerilog and UVM Participate in Low power analysis (UPF), power estimation, C modeling Perform lint, CDC, code coverage, functional coverage Formal verification of modules using SVA assertions Necessary Qualifications Experience in verifying complex subsystems and ASICs Experience with building scalable verification environments from scratch Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc. Exposure to FPGA emulation platforms, silicon bringup, and board debug BTech/MTech in E...

Qualcomm India Private Limited is a leading technology innovator that is committed to pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will play a pivotal role in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on a wide range of components such as yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet p...

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what's possible to create a smarter, connected future for all. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to ensure solutions meet performance requirements. The ideal candidate for this role will have a Bachelor's, Master's, or PhD degree in Computer Science, Electrical/El...

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in ...

We are seeking highy motivated individuas with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to hande the chaenging probems in future technoogies and designs. We are aso ooking for candidates with Strong C/C++background to ead our eading-edge agorithmswithin our EDA soutions to increase our design team’s productivity and chip quaity and performance. Our dynamic goba team is ooking to enist enthusiastic professionas to join word-cass hardware design teams responsibe for deveoping the most chaenging and compex systems in the word. We are seeking energetic, highy motivated individuas wiing to go the extra mie with the aim of heping the overa IBM deveopment team. S...

Job Description: Strong understanding of Physical Design with hands-on experience in RTL2GDS flow. Ability to close tiles/blocks including timing, noise, power, IR, phyV, conformal equivalence, and signoff checks. Exposure to advanced technology nodes (7nm and below) and related design challenges. Experience with the Synopsys tool suite is required. Knowledge of high-frequency design (>2GHz)

Role & responsibilities Leading a team of 3-5 engineers for block-level implementation. Collaborating with a cross-functional team for project planning and completion. Contribute to enhancement of methodologies and flow. Overseeing timing closure, power optimization, and physical verification using industry-standard EDA tools. Managing resources and schedules to ensure timely and quality deliverables. Technical leadership to analyze and debug complex issues and recommend. Supporting and developing best practices in design methodology, quality assurance, and continuous process improvement Preferred candidate profile Experience of Netlist-to-GDS design flow, including floor-planning, placement...

Your Role Implement and configure SAP Document and Reporting Compliance (DRC) in S/4HANA environments. Design scalable solutions for global e-invoicing and statutory reporting. Integrate SAP DRC with FI, SD, and MM modules for accurate compliance. Collaborate with technical teams for interface development and automation. Support legal change management and country-specific compliance updates. Your Profile 4-12 years of SAP functional consulting experience, including SAP DRC (ACR). Strong knowledge of global statutory reporting and e-invoicing frameworks. Hands-on experience with SAP DRC configuration across multiple countries. Proficient in S/4HANA and integration with core SAP modules. Exce...

Responsibilities & Key Deliverables Description of the job and key result areas: Function related: Capability Building of STA domains in platform teams Ensure future readiness by continuously upgrading teams with new technological skills Ensure a Technology roadmap is created along with COE and relevant SSU stakeholders using a structured forum and deploy them to live projects Improvisation of processes and systems through various means such as Digitization, IT enablement, Analytics etc. Create required domain expertise in commodity to help deliver on projects Supplier relationship management Platform related: Manning/Resource Allocation - Enable platform teams to deliver on TCP objectives t...

Responsibilities As a creative Design Constraints Engineer, you will be part of the Front-End Design team, developing, validating , optimizing , and handing off constraints for complex SoCs, ensuring robust timing closure and seamless integration across the various stages of SOC design cycle. Your key responsibilities will include creating and maintaining Design constraints, validating them using industry standard STA tools and handing off to the Implementation teams. You will closely work with the Design team to capture the Design constraints. You will be validating these constraints using industry standard constraint validation tools like Time Vision and other equivalent tools. You will pa...

As Logic Lead, you will be responsible for design and development of Compression, Security, and sustainability features for high performance Processors chips. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature Guide and mentor junior engineers. Represent as Design Lead in various forums. Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Estimate the overall effort to dev...

We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team. Key Responsibilities Work closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPs Carry out floor planning, and physically aware synthesis on high-performance IPs Perform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL team Leads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions...

Job Requirements Role Summary: This is a deep technical leadership role focused on architecting and guiding turnkey SoC physical design projects. The ideal candidate will have extensive hands-on expertise in RTL2GDS implementation at advanced nodes (3nm/5nm), be customer-facing, and capable of owning project methodology, technical quality, and solution engineering end to end. --- Key Responsibilities: Turnkey Delivery Leadership Define and drive end-to-end RTL-to-GDSII flows, tailored for customer-specific technology, tools, and deliverables. Lead complex top-level and hierarchical SoC designs, ensuring quality and signoff compliance. Guide floorplan strategy, power planning, PPA closure, IR...

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills VHDL,RTL coding,Mentor DfT tools,Caden...

4-10 years experience with Bachelors degree in Physical Design for Blre & Hyd Locations Good experience in ICC flow with Innovus tool Knowledgeable in Static Timing Analysis, Power Analysis and Innovus. Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages. Experience in developing PD metrics dashboard scripts for QOR tracking is a plus Experience in modifying STA constraints to check timing closure feasibility Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets Experience in FinFET & Dual Patterning nodes such a...

Alternate Job Titles: ASIC Physical Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced Physical Design Engineer with a passion for implementing and performing signoff verifications of digital blocks using ASIC design flow (Gate2GDSII). You thrive in dynamic environments an...

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills JTAG,ATPG DRC,LBIST,RTL coding,VHDL,DF...

Responsibilities & Achievements: Reduced post-silicon bug escapes through early software-driven validation in emulation environments. (Accelerated Verification) Cut SoC bring-up time by 50% by architecting a unified simulation-to-emulation testbench with reusable transactors. Spearheaded the Accelerated verification plan for a next-gen ADAS SoC including use cases like Start Up, BOOTROM, Complex data path, Negative tests Enabled 80% reuse of verification components across simulation, emulation, and prototype platforms through modular UVM design. Successfully led a AV verification team of engineers across DV, emulation *Mandatory Key Skills ADAS SoC,BOOTROM,simulation,team leadership,Synopsys...

Position: STA (SI30FT RM 3520) Responsibilities will include, but are not limited to: Doing STD cells characterization work (max up to 40% of time) , Static timing analysis (60%) Able to characterize basic STD Cells Writing ARC for STD cell char (using primeLib , Silicon smart) lib QA check Circuit understanding block wise , Full chip level Static timing Analysis of DRAM block wise , top level analysis , cell level analysis Writing constraints , analysing the STA reports Reporting violations to Design team , ownership for closure Parasitic modelling and assisting in design validation, reticle experiments and required tape-out revisions Performing verification processes with modelling and sim...

Cadence is looking for Principal Design Engineer to join our dynamic team and embark on a rewarding career journey Health and Safety Compliance: Ensure that construction projects comply with health and safety regulations, guidelines, and industry standards Risk Assessment: Identify and assess potential health and safety risks associated with the project's design, construction methods, and materials Design Coordination: Collaborate with architects, engineers, project managers, and other stakeholders to integrate health and safety principles into the project's design and planning Hazard Identification: Identify and document potential hazards related to the project, including those arising from...

Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate shoul...

Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate shoul...