Posted:1 day ago|
Platform:
On-site
Full Time
Looking for enthusiastic, motivated and self-driven engineer in area of
Understanding and Defining Chip Power & Performance Targets
Analyzing FSDBs for various design power scenarios and extracting the right activity windows
Running Power Estimation and Analysis at block level and roll-up total power for SoC
Working with Architecture, Design and Implementation teams for power optimization
Running LP checks at block and full chip level, analyzing the logs/reports and deliver quality results
Work closely with the FE & BE teams for overall Power Convergence and Low-Power Sign-off of the design for Tape-out
Intel
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