SoC DFT Design Lead

Job Description

As a member of the S3 SoC DFT Team, the successful candidate will own the DFT SCAN ATPG, Coverage analysis and Silicon bringup Position includes test creation/development, characterization, data analysis, and silicon debug of DFT Scan/ATPG test in leading edge process technologies. AMDs environment is fast paced, results oriented and built upon a legion of forward-thinking people with a passion for winning technology! THE PERSON: A successful person in this role would be able to work in a collaborative team environment working with the RTL designers and other Verification Engineers to find creative ways to accelerate the identification of functional defects Strong self-driving ability, Should have excellent communication skills (both written and oral) Strong problem-solving skills KEY RESPONSIBILITIES: Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT at the SoC level PREFERRED EXPERIENCE: Experience in DFT architecture for complex chips Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration Proficient in doing basic unit-level verification using simulations. Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required. Must have experience with integration of various IPs into complex SOCs. Exposure to Static timing analysis & Timing closure is required. Any prior experience with microprocessor designs is a plus. Scan/ATPG patterns & test flows development, debug, test and characterization Pre-Silicon test planning & validation, Engagement with Design Post Silicon Bring up of test patterns leading to optimization for mass production enablement Characterization and debug of Scan/ATPG test in the new silicon designs and process technologies Optimization of test flows for increased quality and cost improvement Analysis of part failures leading to test coverage and yield improvement Analysis of characterization data across PVT Excellent hands-on debug skills and scripting skills are critical. Must have good communication skills and the ability to work in a worldwide team environment. Knowledge & experience of low power concepts, clock gating, power gating is a plus Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering 8+ years experience in DFT design