Job
Description
As a Silicon Architect/Design Engineer at Google, you will be at the forefront of shaping the future of AI/ML hardware acceleration, specifically focusing on driving cutting-edge TPU (Tensor Processing Unit) technology for Google's most demanding AI/ML applications. Your role will involve collaborating with hardware and software architects and designers to architect, model, analyze, define, and design next-generation TPUs. Your responsibilities will be dynamic and multi-faceted, covering various areas such as product definition, design, and implementation, with a focus on optimizing performance, power, features, schedule, and cost. You will play a crucial role in revolutionizing Machine Learning (ML) workload characterization and benchmarking for next-generation TPUs. Additionally, you will be responsible for developing architecture specifications that align with current and future computing requirements for the AI/ML roadmap. This will involve creating architectural and microarchitectural power/performance models, microarchitecture and RTL designs, and conducting performance and power analysis. Your role will also involve partnering with hardware design, software, compiler, Machine Learning (ML) model, and research teams to facilitate effective hardware/software codesign and develop high-performance hardware/software interfaces. You will be expected to drive the adoption of advanced AI/ML capabilities, implement accelerated and efficient design verification strategies, and leverage AI techniques for optimal Physical Design Convergence, including timing, floor planning, power grid, and clock tree design. Furthermore, you will contribute to the investigation, validation, and optimization of DFT, post-silicon test, and debug strategies, thereby advancing silicon bring-up and qualification processes. Your expertise will be instrumental in contributing to the ongoing development and enhancement of Google's cutting-edge AI models and hyperscale computing platforms. **Minimum Qualifications:** - PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or related technical field, or equivalent practical experience. - Experience with accelerator architectures and data center workloads. - Proficiency in programming languages such as C++, Python, and Verilog, as well as tools like Synopsys and Cadence. **Preferred Qualifications:** - 2 years of experience post PhD. - Experience with performance modeling tools. - Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. - Familiarity with high-performance and low-power design techniques. As a Silicon Architect/Design Engineer at Google, you will be at the forefront of shaping the future of AI/ML hardware acceleration, specifically focusing on driving cutting-edge TPU (Tensor Processing Unit) technology for Google's most demanding AI/ML applications. Your role will involve collaborating with hardware and software architects and designers to architect, model, analyze, define, and design next-generation TPUs. Your responsibilities will be dynamic and multi-faceted, covering various areas such as product definition, design, and implementation, with a focus on optimizing performance, power, features, schedule, and cost. You will play a crucial role in revolutionizing Machine Learning (ML) workload characterization and benchmarking for next-generation TPUs. Additionally, you will be responsible for developing architecture specifications that align with current and future computing requirements for the AI/ML roadmap. This will involve creating architectural and microarchitectural power/performance models, microarchitecture and RTL designs, and conducting performance and power analysis. Your role will also involve partnering with hardware design, software, compiler, Machine Learning (ML) model, and research teams to facilitate effective hardware/software codesign and develop high-performance hardware/software interfaces. You will be expected to drive the adoption of advanced AI/ML capabilities, implement accelerated and efficient design verification strategies, and leverage AI techniques for optimal Physical Design Convergence, including timing, floor planning, power grid, and clock tree design. Furthermore, you will contribute to the investigation, validation, and optimization of DFT, post-silicon test, and debug strategies, thereby advancing silicon bring-up and qualification processes. Your expertise will be instrumental in contributing to the ongoing development and enhancement of Google's cutting-edge AI models and hyperscale computing platforms. **Minimum Qualifications:** - PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or related technical field, or equivalent practical experience. - Experience with accelerator architectures and data center workloads. - Proficiency in programming languages such as C++, Python, and Verilog, as well
