Silicon Architecture/Design Engineer

Role Overview: As a Silicon Architect/Design Engineer at Google, you will play a crucial role in shaping the future of AI/ML hardware acceleration. Your primary responsibility will be to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You will work closely with hardware and software architects and designers to architect, model, analyze, define, and design next-generation TPUs. Your dynamic and multi-faceted responsibilities will include product definition, design, and implementation, collaborating with engineering teams to achieve the optimal balance between performance, power, features, schedule, and cost. Key Responsibilities: - Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. - Develop architecture specifications to meet current and future computing requirements for the AI/ML roadmap. This includes creating architectural and microarchitectural power/performance models, microarchitecture and RTL designs, and evaluating quantitative and qualitative performance and power analysis. - Collaborate with hardware design, software, compiler, machine learning (ML) model, and research teams for effective hardware/software codesign, creating high-performance hardware/software interfaces. - Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. - Utilize AI techniques for faster and optimal Physical Design Convergence, such as timing, floor planning, power grid, and clock tree design. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies to contribute to the advancement of silicon bring-up and qualification processes. Qualifications: - PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or related technical field, or equivalent practical experience. - Experience with accelerator architectures and data center workloads. - Proficiency in programming languages such as C++, Python, and Verilog, as well as tools like Synopsys and Cadence. - 2 years of experience post PhD is preferred. - Experience with performance modeling tools. - Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. - Familiarity with high-performance and low-power design techniques.,