Senior RTL Design Engineer

Work Experience : 4-6 years of industry experience .

Responsibilities Duties

• Participate in next-generation system architecture a full system effort spanning mission planning, software, hardware, and other sub-systems.

• Develop custom IP for new features of the Pixxel camera payload and satellite bus.

• Understand the design requirements, establish the design infrastructure, support verification engineers, and test the correctness of the design.

• Realize high-reliability digital design targeting state-of-the-art Xilinx FPGAs.

• Participate in conceptual design studies of new spacecraft.

Desirable Skills Certifications:

• Comfortable working with Xilinx Vivado Design Suite.

• Experience with external memories (SSD, FLASH, etc.); high-speed transceivers for protocols such as PCIe, SATA; and memory-mapped interfaces such as AXI, Wishbone, Avalon.

• Using advanced design methodologies like Hierarchical Design.

• Experience using lab equipment: high-speed oscilloscopes, logic and protocol analyzers, spectrum analyzers, etc.

• Experience with schematic design and board bring-up is a plus point.

Would be great if you have

• A Bachelors Degree in EE, CS or CE (or a related field) with at least 2+ years of relevant experience or an Advanced Degree (Masters or PhD).

• Excellent knowledge of hardware description languages (Verilog/System Verilog/VHDL).

• Strong understanding of computer architecture and logic design, and serial interfaces SPI, I2C, LVDS, etc.

• Solid understanding of timing principles, including clock domain crossing and timing closure.

• Experience with FPGA tools (e.g Vivado) and HDL Simulation Tools (ModelSim).

• Strong debugging and analytical skills.

• Strong communication skills and the ability to work in a small team are a huge plus.

• Solid programming skills (C / C++, Python, Matlab).

Candidate Acumen:

Benefits: