Senior Designer - ASIC IP

Senior Designer - ASIC IP

What We Offer:

• Creative Freedom:

  Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced design technologies alongside skilled experts.

• Global Impact:

  Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide.

• Work-Life Balance:

  We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life.

• Professional Growth:

  Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere.

What You Will Do: Key Responsibilities

• Develop ASIC IP blocks and subsystems

  , contributing to the advancement of 5G and 6G communication technology.
• Take

  full ownership of a design

  , whether at the block or subsystem level.
• Generate

  comprehensive documentation

  throughout the design lifecycle.
• Perform

  digital design

  and conduct all

  RTL sign-off checks

  .
• Continuously

  enhance and optimize design methodologies and processes

  .
• Collaborate with

  IP Architects

  to break down requirements and create detailed IP architecture and design specifications.
• Work closely with

  verification engineers

  to review and refine verification plans.

• Build competence

  in the technical domain.
• Engage in

  cross-team collaboration

  to ensure successful project delivery.

Required Qualifications:

• Education:

  Bachelor's degree in electrical or computer engineering.

• Industry Experience:

  Proven industry experience in ASIC design.

• Strong Experience in/with:

• Understanding of

  ASIC technology, design environments, and methodologies

  .

• SystemVerilog

  .

• RTL static sign-off tools

  such as SpyGlass.

• Scripting languages

  like TCL, Python, or similar.

• SystemVerilog Assertions

  .

The Skills You Bring: Additional Requirements

• Experience with

  Cadence and Synopsys front-end and middle-end design suites

  .

• Team-oriented

  , prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment.
• High

  attention to detail

  and

  commitment to quality

  .
• Strong focus on

  meeting project deadlines and deliverables

  .
• Proficient in

  English

  , with strong communication skills.

Preferred Skills:

• Understanding of

  radio access systems

  and their components.
• Expertise in

  low-power design

  , including specifying power intent using UPF or similar standards.
• Working knowledge of systems for

  continuous integration

  (e.g., Jenkins),

  simulation and analysis environments

  (e.g., Simscope), and

  issue-tracking

  (e.g., Jira).
• Experience designing one or more of the following hardware domains:

• AMBA-based designs

  especially AXI and CHI.

• ARM-based real-time microcontroller systems

  including their control and interface peripherals.

• Wireless infrastructure specific protocols and interfaces and protocols

  .
• Implementation of

  hardware-based digital signal processing systems

  (filters, adaptation, etc.).