Senior Design Verification Lead (PCIE)

15 years

0 Lacs

Posted:1 week ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

Eximietas Design Hiring Senior Design Verification (PCIE) Engineers / Leads / Managers.

Experience: 5+ to 15 Years.

Location:


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successful execution of verification plans.

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test plans, testbenches, and coverage analysis, for both high-speed and low-

speed peripherals (e.g., I2C, SPI, UART, GPIO, QSPI) as well as high-

speed protocols (e.g., PCIe, Ethernet, CXL, MIPI, DDR, HBM).

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like Xprop and UPF.

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designers, and pre/post-silicon verification teams, to ensure alignment

and seamless integration of verification efforts.

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coverage (code, toggle, functional) to ensure thorough verification of design

functionality.

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helping to elevate team performance.

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collaborative and innovative work environment.

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comprehensive documentation.

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project goals and deadlines.

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continuous improvements in verification methodologies.

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and Xsim.

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enhance verification coverage.


Qualifications:

Minimum 5+ years of hands-on experience in SoC Design Verification.

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I2C/I3C, SPI, UART, GPIO, QSPI, PCIe, Ethernet, CXL, MIPI, DDR, and

HBM.

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coverage.

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Xprop and UPF.

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Cadence.

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managing verification teams.

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collaboration and verification signoff.

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to their continuous improvement.


Preferred Qualifications:

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maruthiprasad.e@eximietas.design

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