Posted:14 hours ago|
Platform:
On-site
Full Time
Job Location: Hyderabad
Notice Period: 15 days to 30 Days
Should have worked on Processor based System or Sub-system level verification
Hands on experience with assembly, UVM, SV, C++
Experience in developing complex test bench/model in UVM, Verilog, System Verilog
Hands on experience in developing test plans, coverage closure
Ability to code readable, maintainable and verifiable code using UVM, SV, Strong digital design concepts
Experience in developing asm/C++ tests will be an added advantage
Experience in Power Management, Clock, Reset will be an added advantage
Experience/Knowledge DPI Interface, Ruby/Perl script programming skills will be an added advantage
ACL Digital
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