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Semiconductor Verification & Simulation Engineer

Semiconductor Verification & Simulation Engineer

Cadfem Engineering Services

5 - 8 years

7 - 11 Lacs

Hyderabad

Posted:1 day ago| Platform:

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Skills Required

Automation Semiconductor DFT Simulation VLSI Analytical Analog Packaging Perl Python

Work Mode

Work from Office

Job Type

Full Time

Job Description

We are seeking skilled engineers to join our semiconductor verification and simulation team. This role focuses on functional, gate-level, DFT, and timing simulations, along with validating SoC and IP blocks. Ideal candidates will have hands-on experience with Synopsys EDA tools, and domain-level knowledge of IC packaging and analog layout design will be a strong plus.

Roles & Responsibilities:

Develop and execute RTL test benches using VCS/SystemVerilog/UVM

Perform functional and gate-level simulation, debug with Verdi

Run DFT pattern simulations, scan insertion validations

Conduct Static Timing Analysis (STA) with PrimeTime

Execute power-aware and multi-mode multi-corner (MMMC) simulations

Validate interfaces considering IC package parasitic (SiP/2.5D/3D-IC understanding is a plus)

Collaborate with teams to correlate package- and board-level effects with chip-level behavior

Analyze analog layout impact on mixed-signal simulation accuracy (awareness of layout parasitic)

Requirements

Strong hands-on experience with Synopsys tools:

VCS (RTL simulation),

Verdi (debug),

PrimeTime (timing),

TetraMAX/TestMAX (DFT),

HSPICE/FineSim (analog simulation exposure is a plus)

Familiarity with IC packaging technologies, chip-package co-simulation, and signal/power integrity considerations

Understanding of analog layout practices and their influence on simulation/verification

Strong scripting skills (TCL, Perl, Python) for automation

Excellent debugging, documentation, and communication skills

Preferred Qualifications:

Bacheloror Masterin Electronics, VLSI, or Electrical Engineering & 5-8 Years of Relevant Experience is mandatory

Awareness of multi-die, chip let, or 3D IC architectures

Basic understanding of EM/IR effects, package substrate modeling, or layout vs schematic (LVS)

Strong analytical and collaborative mindset

Master in VLSI / Microelectronics

Benefits
-Challenging job within a young and dynamic team.

-Performance-driven, Career Progression Opportunities.

-Attractive remuneration package: On par with Industry Standards.

-Opportunity to join an organization experiencing year on year growth.

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Semiconductor Verification & Simulation Engineer