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CPU - NEST Endcap Verification Engineer

CPU - NEST Endcap Verification Engineer

IBM

9 - 14 years

15 - 20 Lacs

bengaluru

Posted:2 days ago| Platform:

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Skills Required

pcie memory subsystem verification vhdl ddr cxl ethernet verilog flash systemc

Work Mode

Work from Office

Job Type

Full Time

Job Description

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers.

Leading the development of the verification environment, testbenches and writing testcases.

Develop skills in IBM Functional verification tools and methodologies.

Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design

Work with development team to ensure coverage criteria is met.

Required education

Bachelor's Degree

Required technical and professional expertise

9 + years of experience in Functional Verification of processors or ASICs.

Minimum 6+ years of experience in any of the following

Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification.

Core architecture/micro-architecture verification

Multi-processor cache coherency, Memory subsystem verification.

IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc

AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification.

Gate level simulation and emulation.

Track record in leading team.

Clock domain crossing and reset domain crossing verification

Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/

Knowledge of HDLs (Verilog, VHDL)

Developed test-plans and test strategies for IP/unit/block level verification.

Good object-oriented programming skills in C/C++, scripting languages like Python/Perl.

Worked on multiple levels of verification (unit/element/sub-system/system level)

Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow

Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails

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CPU - NEST Endcap Verification Engineer