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Role Overview: You have been invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer in Siruseri, Chennai. In this role, you will work directly with a prominent client, contributing to the development of next-generation chip-level verification environments utilizing System Verilog and UVM methodologies. Key Responsibilities: - Conduct functional verification at both block and chip levels for complex designs. - Develop verification test plans based on detailed design specifications. - Construct UVM-based simulation environments using System Verilog. - Perform coverage analysis to ensure validation completeness. - Implement assertion-based verification for functional robustness. - Collaborate across teams to align design and verification milestones. - Work with RAL to validate register-level behaviors. - Create testbenches for simulation and optimize performance efficiency. Qualifications Required: - 6 to 10 years of relevant experience in design verification. - Strong expertise in System Verilog, UVM, and chip-level verification. - Ability to work effectively in a dynamic team environment. - Excellent communication and collaboration skills. - Bachelor's/Master's degree in Electrical Engineering or related field. Company Details: Coventine Digital Private Limited offers a permanent position for a Senior/Lead Design Verification Engineer in Siruseri, Chennai. This is a Work from Office opportunity. Immediate joiners are preferred. Join the team to contribute to cutting-edge chip design projects and shape the future of hardware design while advancing your career in the field of design verification. Apply now by sending your resume to Venkatesh@coventine.com or contacting the company directly. #Hiring #DesignVerification #SystemVerilog #UVM #ChipDesign #ASICVerification #VerificationEngineer #ChennaiJobs #HardwareDesign #CareerGrowth #Recruitment,