560 Rtl Design Jobs - Page 3

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Synthesis. Experience: 3-5 Years.

ASIC RTL DESIGN ENGINEER (4 to 10 Years) IP/SoC Design Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune/Chennai/Noida] Experience: 4 to 10 Years Openings: 6 Positions Job Description Sr RTL Design Engineer We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in designing state of the art solutions for automotive camera and display systems. Responsibilities Microarchitecture definition and RTL implementation ensuring optimal performance, power, area. Collaborate with software teams to define configuration requirements, verification collaterals etc. Work with verification teams on assertions, test plans, debug, coverage etc. Proficiency in Verilog/System Verilog Very google understanding of ASIC design methodologies Qualifications and Preferred Skills Graduate/Post Graduate/PhD in Electrical/Electronics 4-10 years hands-on experience in microarchitecture and RTL development Proficiency in developing micro-architecture from the design requirements, defining the H/W- S/W interface. In-depth understanding of MIPI CSI and DSI protocols Experience designing IP blocks for video and audio design Proficiency in Verilog, System Verilog Familiarity with industry-standard EDA tools and methodologies Experience with large high-speed, pipelined, and low power designs Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Experience in designs complying to automotive functional safety will be a plus

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. This involves working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop innovative solutions. To qualify for this position, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years or a PhD with 2+ years of relevant work experience would be considered. We are seeking bright ASIC design engineers with strong analytical and technical skills to be part of a dynamic team responsible for delivering Snapdragon CPU design for Mobile, Compute, and IOT markets. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be involved in creating design experiments, conducting PPA comparison analysis, and collaborating closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Additionally, developing Place & Route recipes for optimal PPA, tabulating metrics results for analysis, and contributing to the ASIC flow with low power, performance, and area optimization techniques are crucial aspects of this role. The ideal candidate should have 10-15 years of High-Performance core Place & Route and ASIC design Implementation work experience. Proficiency in Place & Route with FC or Innovus, experience with STA using Primetime and/or Tempus, and strong problem-solving skills are preferred qualifications. Knowledge in constraint generation and validation, power domain implementation, formal verification, scripting languages like Perl/Tcl, Python, C++, as well as exposure to Verilog coding and CPU micro-architecture will be advantageous. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. The company's work environment is inclusive and supportive of individuals with disabilities. Applicants should adhere to all relevant policies and procedures, including security measures and confidentiality of company information. Qualcomm does not accept unsolicited resumes or applications from staffing agencies. For more information about this role, please reach out to Qualcomm Careers.,

We are looking for a highly skilled Senior RTL Design Engineer with 8+ years of experience in designing complex digital IPs and SoCs. The ideal candidate should have strong RTL coding, micro-architecture, and synthesis knowledge, with a proven track record of successful tape-outs. Key Responsibilities: Develop RTL code in Verilog/SystemVerilog based on micro-architecture specifications Work on design partitioning, clock domain crossings, and low-power techniques Collaborate with verification, physical design, and DFT teams across the design cycle Perform lint, CDC, and synthesis with timing constraints Optimize design for area, performance, and power Participate in design reviews and documentation Requirements: 8+ years of RTL design experience in ASIC/SoC development Strong knowledge of digital design principles and SoC architecture Hands-on experience with RTL design tools (SpyGlass, Design Compiler, etc.) Experience with AMBA protocols (AXI, AHB, APB), FIFOs, arbiters, and bus interfaces Exposure to synthesis, STA constraints, and backend handoff Strong debugging, problem-solving, and communication skills How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are also looking for candidates with Strong C/C++background to lead our leading-edge algorithmswithin our EDA solutions to increase our design team’s productivity and chip quality and performance. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMerCome THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4+ years of IT experience Strong C/C++programming skills in a Unix/Linux environment is a must. VLSI knowledge, Knowledge in front end linting tools and checkers and RTL Checkers. Great scripting skills – Perl / Python/Shell Proven problem-solving skills and the ability to work in a team environment are a must Preferred technical and professional experience RTL Lint Checkers , Front end verification flow, VLSI knowledge, VHDL/Verilog, computer architecture

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal methodology, Knowledge of HDLs (Verilog, VHDL, SV), Good programming skills in python, processor core u-arch skills Exposure in developing testbench environment, debugging and triaging fails. Good communication skills and be able to work effectively in a global team environment. Drive verification coverage closure, lead verification team. Drive complex scenarios, participate in High level design discussions. Track record in leading teams. Preferred technical and professional experience Writing test plans, building random / exhaustive formal verification environment, functional and coverage analysis and debug. Good understanding of the Server System

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

THE ROLE: The Infinity Fabric transport layer verification team is looking for an experienced pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. Our growing team needs additional senior engineering experience to help us enhance our configurable testbench and to mentor junior engineers. THE PERSON: The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment. KEY RESPONSIBILITIES: Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Understand TestBench Architecture and develop expertise in TestBench Verification Components. Mentor junior engineers. PREFERRED EXPERIENCE: Proficient in IP or Sub-system level ASIC verification Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar. Exposure to RTL design, software development, formal verification, or other related domains. Experience in UVM TestBench Development for complex designs preferred. Experience in RAL is preferred

THE ROLE: We are looking foran adaptive, self-motivated SoC Front-end Design Engineer to join our growing team. As a key contributor,you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. THE PERSON: You have a passion for modern, complex processor architecture, digital design, SOC design, design quality checks and design automation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Design of Subsystems with integration of AMD and other 3rd party IPs Understand clocking, reset and soc top level topology changes to make connectivity as per the topology across IPs Collaborate with architects, Verification engineers, and Physical design Engineers to understand the new features to be designed and integrated in SoC Understand SOC power domain requirements(power architecture) to write UPFs Perform quality checks: Lint, CDC, Low Power checks, Timing constraints, LEC for complex digital designs Identify areas for automation and create solutions to improve productivity and quality, continuously improve the automation process by exploring new tools and technologies PREFERRED EXPERIENCE: Minimum 10 years of RTL design, Architecture, SOC implementation experience Proficient in Verilog and System Verilog with good understanding of RTL design flows and process Detailed understanding of SoC design flows Experience with version control system such as perforce Verilog lint(Spyglass) and simulation tools (VCS) Good understanding and hands-on experience in CDC, RDC, Timing constraints, LECand other design quality check concepts Knowledge on UPF, Low Power design, IP/SS/SOC Power Management(PM) techniques(Power Gating, Clock Gating) and Low Power static analysis checks will be added advantage Good with Scripting languages such as Python, Perl, Makefile, TCL and unix shell Automating workflows in a distributed compute environment Experience with embedded processors, data fabric architectures (NoC) and standard protocols such APB/AXI Stream and AXI MM Ability to work with multi-level functional teams across various geographies Strong problem-solving and analytical skills ACADEMIC CREDENTIALS: B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering with Digital Systems/VLSI as major.

THE ROLE: The focus of this role is to plan, build, and execute DFT verificationfor AMD's next generation Zen-architecture based CPU cores THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop and execute pre-silicon verification testplans for DFT features of the nextgeneration Zen-architecture based CPU Cores Develop directed and random verification tests to fully validate DFT functionality Verify DFT design blocks and subsystems (such as JTAG/1500/1687, MBIST, Fuse, Clocks, Resets, etc.)using complex SV or C++ verification environments. ConstructSystem Verilog and/or C/C++ models and test sequence libraries for simulation. Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives. Collaborate with architects and hardware engineers, to understand the new features to be verified Estimate the time required to write the new feature tests and any required changes to the test environment Debug test failures to determine the root cause; work with RTL engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements Post silicon ATE and System level debug support of the test patterns delivered PREFERRED EXPERIENCE: Proficient in IP/SoClevel ASIC verification Proficient in debugging RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Developing UVM based verification frameworks and testbenches, processes and flows CPU architecture knowledge is desirable Automating workflows in a distributed compute environment. Scripting language experience: Perl, Ruby, Makefile, shell preferred. DFT knowledge on Memory BIST, Logic BIST, Scan, ATPG is highly desirable Exposure to leadership or mentorship is an asset

THE ROLE: We are seeking individuals with a desire to address challenging problems on daily basis. Virtual Bring-Up (VBU) is a premiere central methodology team that strives towards excellence, utilizes novel industry technologies and comes up with innovative ways to address execution challenges. THE PERSON: As part of VBU, you will work across AMD's product portfolio to develop and enable methodology and tools to tackle key design cycle challenges for the company by leveragingacceleration, hardware emulation and prototyping technologies. You will have a serious level of opportunity to learn, grow and excel in this role. KEY RESPONSIBILITIES: Develop and deploy FPGA-based prototyping methodologies across AMD business units Work with customer teams across AMD's business units to enable recommended methodologies, as well as improve execution and efficiency Drive standardization and automation across business units and technology platforms Responsibilities will include support and development as needed of FPGA prototyping build and regression infrastructure and continuous integration methodologies PREFERRED EXPERIENCE: Computer Hardware design, development or verification background Experience with RTL design simulation and verification FPGA prototyping or relevant emulation platform experience Good understanding of computer architecture and FPGA synthesis Experience with scripting languages (Python, Tcl, Perl, shell scripting, makefiles) Working knowledge of board design and debug Strong problem solving skills and methodical work practices BIOS firmware and low-level software debug experience is desirable Knowledge of physical interfaces such as PCIe, DDR/LPDDR/GDDR memory, USB, ethernet, I2C/SPI and JTAG is desirable Virtual Motherboard/Platform experience is a big plus ACADEMIC CREDENTIALS: Bachelor's orMaster'sdegree in Computer or Electrical Engineeringor equivalent

THE ROLE: As a member of the Client Group, you will help bring to life cutting-edge designs.?As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. The Person: If you have a knack for power saving techniques, including clock gating and UPF-based power gating, this role is for you. You will be responsible for generating Power spec, UPF, performing quality checks of power-gated digital designs,execute the SoC RTL integrationand working collaboratively with the IP team. Key Responsibilities: Understanding of IP/SS/SoC Power Management(PM) techniques. Converting PM Specification to UPF Perform low power quality checks VSI/VCLP Debugging experience on Power aware simulation (NLP sim) Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including UPF, verification, Power sequence, and post-silicon bring-up Need to understand clocking, reset and soc top level topology changes to make connectivity as per the topology across Ips. Need to understand the requirements of power domain(power architecture) to write UPFs. Collaborate with architects, DV and PD engineers to understand the new features to group the logic into tiles based on functionality as well as PD FP requirements. Must have been expert with RTL coding and other Debug capabilities. Preferred Experience: 7+ years full-time experience in IP/SOC hardware design Experience doing ECOs Experience with power aware CDC runs Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Experience with RTL Quality Checks - Verilog lint tools (Spyglass), verilog simulation tools (VCS) and Clock domain crossing (CDC) tools Proficient in IP level ASIC or SoC level RTL integration work and verification Good understanding and hands-on experience in the Timing, UPF, CDC, RDC and other quality check concepts Proficient in debugging RTL code using quality check and simulation tools. Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills Exposure to leadership or mentorship is an asset. ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

MTS Product Engineer The Product Engineer position is in the Customer Enablement and Success group, located in Hyderabad, Telangana, India, for an experienced application engineer to focus on FPGA & ACAP design methodologies, compilation flows, design closure ease-of-use, tools specification, validation, documentation and key customers support. As a member of a highly seasoned Product Development Engineering team, the successful candidate will work closely with several R&D teams, internal application design teams and tier-1 customers to improve the user experience and productivity and enable the next generation of high performance computing designs across the UltraScale and Versal ACAP device families. Daily activities will include the following duties: Own a Vivado product area and become the future team champion to work on high impact projects and with key customers. Drive critical customer escalations to closure and contribute to new technologies rollout. Contribute to triaging reported issues in several Vivado product areas, such as design entry, NoC and IP design flows, compilation, and help engineering address them effectively. Actively explore innovative methodologies and their impact on flow and design practices for the new 7nm Versal ACAP family. Work closely with AMD Business Units (Data Center, Wired, Wireless, Emulation & Prototyping, Test Equipment) to improve their designs, products and customer experience. Develop and deliver training materials on new features and methodologies. Stay current with and propose the internal use of industry approaches, algorithms, and practices Education and Experience Requirements MS or equivalent work experience in Electrical Engineering or similar technology area, with minimum 8 years of relevant experience. Customer Awareness: Has excellent working knowledge of RTL-based design flows and expectations. Product Knowledge: Has good working knowledge of the entire FPGA or ASIC design process and tool flow, with intermediate-to-advanced understanding in timing analysis and closure. Scripting experience (Tcl, Perl, Python) is desired. Design Enablement: Has good understanding of design methodologies for system design, AXI protocol, network-on-chip, design closure. Problem Solving: Ability to handle and solve complex system level issues. Technical Communication: Can simplify and communicate even the most complex subjects, making options, tradeoffs, and impact clear. Can report out to management in a concise and actionable manner. Teamwork : Able to work with several teams across sites and domains with a positive attitude under variable workloads.

Lead ASIC Security Design Verification Engineer Position Overview We are seeking a Lead ASIC Security Design Verification Engineer to drive verification strategy and lead a team of engineers. The role involves architecting verification environments, mentoring team members, and ensuring robust security implementations in complex ASIC designs. Essential Responsibilities Lead and manage a team of design verification engineers Define and drive verification methodology and strategy for security-focused ASIC projects Architect advanced verification environments using UVM methodology Review and approve verification plans, test scenarios, and coverage metrics Guide technical decisions for verification infrastructure and framework development Establish best practices for security verification across projects Drive cross-functional collaboration with design, software, and product teams Provide technical leadership in verification reviews and project meetings Mentor and develop team members technical and professional growth Required Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field 10+ years of Hardware Engineering experience with at least 5 years in lead verification roles Proven track record of leading complex verification projects and teams Expert-level knowledge in RTL design verification using Verilog/System Verilog/UVM methodology In-depth understanding of security protocols and cryptographic implementations: Symmetric and asymmetric cryptography Public/private key infrastructure Hash functions and random number generators Encryption/signature algorithms (AES, SHA, GMAC) Inline cryptography Advanced programming skills in Verilog, C/C++, Python, and Perl Strong experience in verification planning and coverage-driven verification Exceptional problem-solving and debugging skills Outstanding leadership and communication abilities Preferred Qualifications Master's degree in Electrical Engineering Experience leading security-critical tape-outs Expertise in hardware security architecture and threat modeling Knowledge of formal verification methodologies Experience with verification IP development and reuse strategies Track record of implementing verification process improvements Publications or patents in hardware security or verification Leadership Competencies Proven ability to build and lead high-performing technical teams Excellence in project planning and execution Strong decision-making and problem-solving abilities Effective stakeholder management skills Ability to mentor and develop team members Strategic thinking and innovation mindset Technical Leadership Establish verification standards and methodologies Drive adoption of new verification technologies and tools Lead technical reviews and design discussions Guide architectural decisions for verification environments Contribute to organizational verification strategy

PREFERRED EXPERIENCE: ? B.E/M.E/M.Tech or B.S/M.S in EE/CE with 8+ years of relevant experience Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges Circuit timing/STA, and practical experience with tools Working knowledge of C; embedded experience a plus Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards Been exposed to memory controller and PHYs from different IP vendors Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software Version control systems such as Perforce, ICManage or Git Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: ? Bachelors orMastersdegree in computer engineering/Electrical Engineeringwith 8+ yrs of exp

THE ROLE: The person will be part of AMD's Server SoC Performance Validation team. This team is part of AMD's global Server SoC Performance teams and plays a critical role in next generation AMD Server SoC design. Involves having deep understanding of existing AMD X86 SoC architecture/microarchitecture including CPU/ Cache Hier, Memory Subsystem and IO subsystem; debugging performance issues of RTL, giving feedback to design team for latest gen SoC in pre-silicon and emulation environment. We highly encourage people with a creative bent of mind and with a natural ability to dive into the details. This team is a perfect place for people who can understand the present and envision the future. If you find yourself to be a person who wants to go that extra mile to refine an existing process and also understands the opportunities to make it better, if you are the one who has innovative ideas in your brain waiting to find a proper stage to come out, we can offer you the perfect ground for that. THE PERSON: Should have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment. Continuous learning has always been the moto in this ever changing industry. An ideal person for this role should be a self-learner and always ready to upgrade his/her skills to stay abreast with the technology. The team looks for superstars but also believes in nurturing you into one. Collaboration is the key to success. Ideal candidate should learn at a great pace, deliver what is expected and also share your learning in the team to help the overall growth. It's always We before Me in the team KEY RESPONSIBILITIES: Responsible for building infrastructure for performance verification and verify performance of X86 SoC. Performance verification at full chip env involves Core Subsystem ,Memory Subsystem and IO Subsystem perf verification. Writing specific targeted tests to measure the performance of the Server SoC In coordination with Perf architects,driving tuning of performance results to meet product bounding box Involves having a deep understanding of SoC micro-architecture and triaging performance issues in RTL and simulator Skillset Debug triage of failures from simulation and emulation environment for SoC or sub level regressions. Writing automatized triages in Perl/Ruby and creating tools using perl/ruby or AMD verification methodology (primarily in C++) to enhance the functional debug and triage process. On a need basis, work on Post-Si bug recreation. PREFERRED EXPERIENCE: Experience: 10-18 years experience in processor/ASIC performance correlation. Experience in micro-architecture testing for modern high-performance processors. Experience in writing tests and building infrastructure that tests performance of modern processors. Experience in application performance analysis Programming/Scripting Skills C, C++, Perl, Python. Solid background and understanding of Digital Design, RTL design , improving model performance and Processor Architecture Strong troubleshooting, analytical and debug skills. Prior experience in performance correlation of Processor subsystems is a plus. Excellent knowledge of computer architecture with relevantresearch and project work or industry experience Strong programming skills (C/C++ and assembly) Basic knowledge of Verilog ACADEMIC CREDENTIALS: Bachelors/Masters in Computer Science/Electrical/Electronics Engineering with relevant course and research work

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: The person will be part of AMD's CPU Performance Validation team. This team is part of AMD's global CPU Performance teams and plays a critical role in next generation AMD CPU design. Involves having deep understanding of existing AMD X86 CPU architecture and microarchitecture ranging from CPU pipeline stages to various complex features and structures, debugging performance issues of RTL, giving feedback to design team for latest gen CPU in pre-silicon and emulation environment. We highly encourage people with a creative bent of mind and with a natural ability to dive into the details. This team is a perfect place for people who can understand the present and envision the future. If you find yourself to be a person who wants to go that extra mile to refine an existing process and also understands the opportunities to make it better, if you are the one who has innovative ideas in your brain waiting to find a proper stage to come out, we can offer you the perfect ground for that. THE PERSON: Should have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment. Continuous learning has always been the moto in this ever changing industry. An ideal person for this role should be a self-learner and always ready to upgrade his/her skills to stay abreast with the technology. The team looks for superstars but also believes in nurturing you into one. Collaboration is the key to success. Ideal candidate should learn at a great pace, deliver what is expected and also share your learning in the team to help the overall growth. It's always We before Me in the team KEY RESPONSIBILITIES: Responsible for building infrastructure for performance verification and verify performance of X86 processor. Writing specific targeted tests to measure the performance of the processor Involves having a deep understanding of processor micro-architecture and triaging performance issues in RTL and simulator Skillset Debug triage of failures from simulation and emulation environment for CORE or sub level regressions. Writing automatized triages in Perl/Ruby and creating tools using perl/ruby or AMD verification methodology (primarily in C++) to enhance the functional debug and triage process. On a need basis, work on Post-Si bug recreation PREFERRED EXPERIENCE: Experience: 3-15 years experience in processor/ASIC performance correlation. Experience in micro-architecture testing for modern high-performance processors. Experience in writing tests and building infrastructure that tests performance of modern processors. Experience in application performance analysis Programming/Scripting Skills C, C++, Perl, Python. Solid background and understanding of Digital Design, RTL design , improving model performance and Processor Architecture Strong troubleshooting, analytical and debug skills. Prior experience in performance correlation of Processor subsystems is a plus. Excellent knowledge of computer architecture with relevantresearch and project work or industry experience Strong programming skills (C/C++ and assembly) Basic knowledge of Verilog ACADEMIC CREDENTIALS: Bachelors/Masters in Computer Science/Electrical/Electronics Engineering with relevant course and research work

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIORSILICON DESIGN ENGINEER THE ROLE: We are looking foran adaptive, self-motivative design engineer to join our growing team. As a key contributor,you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The DesignEngineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, SOC design, design quality checks and design automation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Design of Subsystems with integration of AMD and other 3rd party IPs Understand clocking, reset and soc top level topology changes to make connectivity as per the topology across IPs Collaborate with architects, Verification engineers, and Physical design Engineers to understand the new features to be designed and integrated in SoC Understand SOC power domain requirements(power architecture) to write UPFs Perform quality checks: Lint, CDC, Low Power checks, Timing constraints, LEC for complex digital designs Identify areas for automation and create solutions to improve productivity and quality, continuously improve the automation process by exploring new tools and technologies PREFERRED EXPERIENCE: Proficient in Verilog and System Verilog with good understanding of RTL design flows and process Detailed understanding of SoC design flows Experience with version control system such as perforce Verilog lint(Spyglass) and simulation tools (VCS) Good understanding and hands-on experience in UPF, CDC, RDC, Timing constraints, LECand other design quality check concepts Good with Scripting languages such as Python, Perl, Makefile, TCL and unix shell Automating workflows in a distributed compute environment Experience with embedded processors, data fabric architectures (NoC) and standard protocols such APB/AXI Stream and AXI MM Ability to work with multi-level functional teams across various geographies Strong problem-solving and analytical skills ACADEMIC CREDENTIALS: B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering with Digital Systems/VLSI as major.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs.?As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of DesignforTest methodologies and DFT verificationexperience (eg.IEEE1500, JTAG 1149.x, Scan, memory BISTetc.) Experience with Mentortestkompressand/or SynopsysTetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering.

You are a talented and experienced Micro-architect RTL Engineer who will join a dynamic team. You have a strong background in multiple technologies and exposure to ARM or microprocessor design and networking. With over 10 years of experience, you will design and implement RTL microarchitecture for high-performance processors, optimizing components for efficient execution and low-power consumption. Your collaboration with cross-functional teams will help achieve project goals, including performance analysis and optimization of designs. You will also contribute to verification plans and methodologies, staying updated with industry trends. As a qualified candidate, you hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Your extensive experience in RTL design using VHDL, Verilog, or System Verilog, along with a proven track record in microarchitecture design, makes you a valuable asset. Your familiarity with ARM or microprocessor design, networking concepts, and protocols, coupled with proficiency in design and simulation tools, helps you excel in this role. Your problem-solving skills, attention to detail, and communication abilities are essential for success. Preferred qualifications include experience with low-power design techniques, formal verification, and validation methodologies. Knowledge of scripting languages like Python or Perl is beneficial for automation purposes. In return, you will be part of a collaborative and innovative work environment with opportunities for professional growth and development. A competitive salary and benefits package await you as you work on cutting-edge technology projects that have a real impact. If you are interested in this opportunity, please share your updated resume at maruthiprasad.e@eximietas.design. The position is available in Bangalore & Visakhapatnam.,