RTL/Firmware Design Engineer

As a RTL/Firmware Design Engineer at our advanced technology company, you will play a crucial role in merging traditional hardware design with cutting-edge AI technologies. Your responsibilities will include: - Designing and verifying RTL for custom logic in FPGAs or ASICs through testbenches or FPGA prototypes. - Developing embedded firmware in C/C++ or Rust to support hardware functionality and validation. - Utilizing tools like Cursor and Windsurf for exploring RTL design spaces and aiding in floorplanning, synthesis, and physical design optimization. - Leveraging Deep Reinforcement Learning to automate and enhance RTL-related tasks. - Designing and implementing Graph Neural Networks (GNNs) for learning representations of circuits, netlists, or control/data flow graphs. - Building AI agents using PyTorch, Hugging Face, and RL libraries like RLlib, Stable-Baselines3, or CleanRL. - Collaborating with the team to develop innovative AI-augmented hardware design workflows. - Contributing to internal tools and libraries that integrate ML/AI with RTL and firmware workflows. To be successful in this role, you should possess the following qualifications: - 3-6 years of hands-on experience in RTL design and firmware development. - Proficiency in Verilog and SystemVerilog. - Experience with embedded software development in C/C++ or Rust. - Familiarity with FPGA or ASIC development flows, including synthesis, place and route, and timing closure. - Practical experience using Cursor, Windsurf, or similar hardware exploration tools. - Python programming skills and deep knowledge of PyTorch. - Solid understanding of Deep Reinforcement Learning and hands-on experience with RL frameworks. - Exposure to Graph Neural Networks (GNNs) and their application in structured data or graph-based modeling. - Experience with RTL simulation frameworks like Verilator or cocotb. It would be nice to have experience in applying AI/ML to EDA problems such as floorplanning, verification, testbench generation, or synthesis optimization. Additionally, familiarity with ONNX, TorchScript, or exporting ML models for runtime integration, as well as contributions to open-source ML/EDA/hardware projects or relevant research publications, are considered advantageous.,