Posted:1 week ago| Platform: Linkedin logo

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Skills Required

design engineering verification test dft emulation layout data learning analytics iot mobile management network verilog architecture integration coding

Work Mode

On-site

Job Type

Full Time

Job Description

TITILE: RTL DESIGN ENGINEER (Principal/Senior Staff/Staff Engineer)


Location: Bangalore/Hyderabad


EXPERIENCE: 4 years to 15 years


ABOUT COMPANY:

SmartSoC Solutions is a

Our expertise is in SOC Design & Verification, Physical Design & Verification, Design for Test DFT), FPGA Design & Emulation, Analog Design & Layout, Artificial Intelligence, Data Science, Machine Learning, Deep Learning, Data Analytics, IoT, M2M, ATMP services, Product Engineering, Digital Solutions (Web, Mobile, Cloud, Custom Applications), Infrastructure Management, Network and Cyber Security.

Our niche skill pool of 1400+ Scientists & Engineers are doing exceptional work across offices in multiple cities in India, USA, Sweden, Finland, South Korea, Malaysia, Canada and Israel. We are continuously expanding our global presence. We follow world-class Engineering practices and Standards with an unwavering focus on disruptive innovation!


ROLES AND RESPONSIBILITIES:

-RTL design in Verilog/SystemVerilog

-Micro-architecture, integration & debug

-Synthesis-friendly coding practices

-Experience in ASIC SoC designs



Contact:

Sumit S. B.

sumit@mulyatech.com

Mulya Technologies

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