Hybrid
Full Time
• Work together with system architects and micro architects to define high level specifications
that are implementable.• Contribute to RTL development including running tool flows like lint, CDC, Conformal lowpower and DFT checks• Work closely with functional verification teams on test-plan development and debug.• Understand timing constraints, run synthesis and deliver synthesized netlist to PD team andprovide constraints support for PD teams.• UPF writing, power aware equivalence checks and low power checks.• Collaborate with other functional teams including DFT, physical design and emulation teamsto achieve project milestones.• Provide support to functional validation teams in post silicon debug.
• MTech/BTech in EE/CS with hardware engineering experience of 1 to 15 years.
• Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA• Experience in Microcontroller and Microprocessor architecture, Interconnect, CacheCoherency.• Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) andmemory controllers.
• Strong domain knowledge of clocking, system modes, power management, debug, security
and other architectures is a must.• Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe,Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memorysubsystems.• Experience with post-silicon bring-up and debug is a plus.• Able to work with teams across the globe and possess good communication skills
Randstad
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