RTL Design Engineer FPGA

2 - 7 years

5 - 12 Lacs

Posted:20 hours ago| Platform: Naukri logo

Apply

Work Mode

Work from Office

Job Type

Full Time

Job Description

RTL Design Engineer

Key Responsibilities:

  • RTL coding using

    Verilog, SystemVerilog, or VHDL

  • Work on

    FPGA architecture and flow

    , including logic and digital design
  • Scripting with

    Tcl and Python

  • Perform synthesis and design stages using

    Vivado

  • Collaborate with design teams to deliver high-quality IP blocks for FPGA

Mock Interview

Practice Video Interview with JobPe AI

Start Python Interview
cta

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.

Job Application AI Bot

Job Application AI Bot

Apply to 20+ Portals in one click

Download Now

Download the Mobile App

Instantly access job listings, apply easily, and track applications.

coding practice

Enhance Your Python Skills

Practice Python coding challenges to boost your skills

Start Practicing Python Now
Coventine Digital logo
Coventine Digital

Digital Marketing

Marketing City

RecommendedJobs for You