Principal Engineer Design Verification Methodologies

Responsibilities:

• Lead the development and deployment of sophisticated front-end methodologies for ASIC design, including Verification, SoC Integration, LEC, and Implementation processes.
• Drive and deliver customer-centric automation and tool development initiatives in collaboration with IT and software teams.
• Lead all aspects of migration strategies for major EDA tool transitions (e.g., CDC 0in to SpyGlass, RealIntent RDC to VC RDC).
• Collaborate closely with worldwide vendor R&D and AE teams to evaluate and deploy AI and automation solutions for ASIC workflows.
• Orchestrate RTL quality improvement initiatives including CDC SVA-based verification, Lint optimization, and formal verification improvements.
• Own vendor management responsibilities, including SOWs, important metric tracking, license management, tool evaluation, and documentation.
• Represent the company in technical conferences, working groups, and internal award forums.

Required Skills and Experience :

• 15+ years of experience in VLSI ASIC design, verification, and methodology development.
• Confirmed leadership in setting up and handling high-performance teams and engineering charters.
• Expertise in EDA tools such as SpyGlass, VC RDC, LEC, Design Compiler, VCFSM, and formal verification tools.
• Proficiency in scripting and automation using Python, Perl, TCL.
• Strong understanding of Verilog/SystemVerilog and front-end design verification techniques (CDC, Lint, FV).
• Experience with tool migrations and performance benchmarking.
• Solid background in multi-functional collaboration with software, IT, and program management teams.
• Exceptional communication, collaborator management, and technical program leadership.

• Experience with AI flow optimization and automation in EDA environments.
• Familiarity with automotive and compute SoC programs and compliance processes.
• Awards or accolades demonstrating innovation, execution excellence, and peer recognition.