10 - 15 years
10 - 15 Lacs
Posted:1 day ago|
Platform:
On-site
Full Time
Write high-level architecture specifications. Design and implement low power techniques including RTL and UPF design Lead PPA analysis and power modeling to determine design tradeoffs Perform synthesis and timing what-if analysis Develop and automate low power design flows in collaboration with cross-functional teams Minimum Qualifications Experience: M.Sc. Degree in Electrical Engineering, Computer Science, or Computer Engineering, with 10+ years of experience Experience in low power design and methodology in advanced technology nodes Excellent technical and analytical background with problem-solving skills Great team worker with multi-discipline, multi-cultural and multi-site environments Strong scripting and flow automation skills (Shell, TCL and Python) Strong RTL development experience in HDL programming languages (Verilog / SystemVerilog) Experience in Digital Design Flow including synthesis and static timing analysis In-depth understanding of low power design techniques such as power gating, clock gating, state retention, near-threshold computing, etc Excellent written and verbal communication Preferred Qualifications Experience: PhD in Electrical and Computer Engineering Experience in Cadence Suite (Virtuoso ADE Spectre) Experience in System-C and Platform Architect Experience in PDN or IR analysis Experience in SPICE simulation
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