7 Low Power Jobs

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. This involves working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop innovative solutions. To qualify for this position, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years or a PhD with 2+ years of relevant work experience would be considered. We are seeking bright ASIC design engineers with strong analytical and technical skills to be part of a dynamic team responsible for delivering Snapdragon CPU design for Mobile, Compute, and IOT markets. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be involved in creating design experiments, conducting PPA comparison analysis, and collaborating closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Additionally, developing Place & Route recipes for optimal PPA, tabulating metrics results for analysis, and contributing to the ASIC flow with low power, performance, and area optimization techniques are crucial aspects of this role. The ideal candidate should have 10-15 years of High-Performance core Place & Route and ASIC design Implementation work experience. Proficiency in Place & Route with FC or Innovus, experience with STA using Primetime and/or Tempus, and strong problem-solving skills are preferred qualifications. Knowledge in constraint generation and validation, power domain implementation, formal verification, scripting languages like Perl/Tcl, Python, C++, as well as exposure to Verilog coding and CPU micro-architecture will be advantageous. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. The company's work environment is inclusive and supportive of individuals with disabilities. Applicants should adhere to all relevant policies and procedures, including security measures and confidentiality of company information. Qualcomm does not accept unsolicited resumes or applications from staffing agencies. For more information about this role, please reach out to Qualcomm Careers.,

As a Lead Analog Validation Engineer, you should have a minimum of 7 years of experience and hold a Bachelors or Masters degree in Electronics or Electronics & Communication. Your expertise should include a strong understanding of electrical circuit analysis, design, and test fundamentals. You must be proficient in automating Analog Characterization Setups using Labview and Test Stand, and have strong debugging and problem-solving skills. Your responsibilities will include bringing up Silicon & Analog Validation Platforms for new ASIC/SoC designs, developing bench characterization test methodologies for various Analog IPs such as ADC, DAC, PLL, USB, VREG, OSC, DDR, LOW POWER, and IO PADs. You will also be required to develop automated code to control test equipment and generate required PVT electrical parameters. Additionally, you should possess expertise in using test & measurement equipment for Analog Validation, PVT characterization of Analog IPs, and have experience in Multilayer Board design, testing, integration, and Signal Integrity issues. Knowledge of C programming is essential for this role. Strong leadership and planning skills are crucial as you will be expected to deliver timely results in lead positions. You will work closely with cross-functional teams including marketing, systems, design, test, and project management to support the successful launch of new products. Your ability to communicate effectively with individuals from diverse backgrounds and strong team-building skills are essential for this role. Your motivation and energy to tackle bench characterization challenges on stand-alone/automated setups will be key to success in this position.,

The ideal candidate for this position should have at least 7+ years of experience in the field. The location for this role includes Bangalore, Delhi NCR, and Hyderabad with 8-10 openings available. The preferred education qualifications are BE/B.Tech./MS/M.Tech. in Electronics or Electronics & Communication. **Required Basic Qualification & Skills:** - Strong understanding of electrical circuit analysis, design, and test fundamentals - Automation of Analog Characterization Setups using Labview and Test Stand - Strong debugging and problem-solving skills - Experience in bring up of Silicon & Analog Validation Platforms - Proficiency in C programming - Leadership and planning skills for timely results delivery **Additional Preferred Qualifications:** - Expertise in using test & measurement equipment for Analog Validation - PVT characterization experience of Analog IPs like ADC, DAC, PLL, USB, VREG, OSC, DDR, LOW POWER, and IO PADs - Good debugging exposure and root cause analysis for new analog designs - Knowledge of Multilayer Board design, testing, integration, and Signal Integrity issues - Experience with LabVIEW and Test Stand automation software - Working experience in a lab environment **Primary and Secondary Responsibilities:** - Develop unique bench characterization test methodologies for Analog IPs - Write automated code for controlling test equipment during data collection and processing - Perform Design Evaluation and Bench Characterization for Analog IPs - Provide requirements and review schematics for circuit board development **Other Complex Tasks:** - Provide customer application note support by generating characterization data - Collaborate with cross-functional teams for successful product launches **Team and People Skills:** - Strong team-building skills and effective communication abilities are essential for this role.,

Qualcomm India Private Limited is a leading technology innovator that aims to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. The ideal candidate should possess strong analytical and technical skills, especially in ASIC design. Responsibilities for this position include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be expected to create design experiments, conduct detailed PPA comparison analysis, collaborate with various teams for optimization, and develop Place & Route recipes for optimal PPA results. Qualifications required for this role include 6-15 years of experience in High-Performance core Place & Route and ASIC design Implementation. Preferred qualifications involve extensive experience in Place & Route with FC or Innovus, knowledge of complete ASIC flow with optimization techniques, proficiency in STA using Primetime and/or Tempus, and skills in Perl/Tcl, Python, C++, among others. Problem-solving abilities, experience with CPU micro-architecture, low power implementation techniques, and clock tree implementation techniques are also desired. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If accommodation is needed during the application/hiring process, individuals can contact Qualcomm for support. The company expects its employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised that only individuals seeking a job at Qualcomm should use the Careers Site. Unsolicited submissions from agencies will not be accepted. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

Write high-level architecture specifications. Design and implement low power techniques including RTL and UPF design Lead PPA analysis and power modeling to determine design tradeoffs Perform synthesis and timing what-if analysis Develop and automate low power design flows in collaboration with cross-functional teams Minimum Qualifications Experience: M.Sc. Degree in Electrical Engineering, Computer Science, or Computer Engineering, with 10+ years of experience Experience in low power design and methodology in advanced technology nodes Excellent technical and analytical background with problem-solving skills Great team worker with multi-discipline, multi-cultural and multi-site environments Strong scripting and flow automation skills (Shell, TCL and Python) Strong RTL development experience in HDL programming languages (Verilog / SystemVerilog) Experience in Digital Design Flow including synthesis and static timing analysis In-depth understanding of low power design techniques such as power gating, clock gating, state retention, near-threshold computing, etc Excellent written and verbal communication Preferred Qualifications Experience: PhD in Electrical and Computer Engineering Experience in Cadence Suite (Virtuoso ADE Spectre) Experience in System-C and Platform Architect Experience in PDN or IR analysis Experience in SPICE simulation

Understanding of GPU power and clock domains with power-up/down sequences Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging simulations and achieving all coverage goals Develop test plan to verify sequences and design components for Clock and power management modules. Explore innovative DV methodologies (formal and simulation ) to continuously push the quality and efficiency of test benches Successful candidatewill be required to collaborate with worldwide design, silicon and architecture teams to achieve all project goals. Hence, we are looking for candidates with strong communication skills. Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications Minimum 3 -13 years of design verification experience * Senior positions to be offered to candidates with proven expertise in the relevant field Preferred Qualifications * 3+ years industry experience with below skillset : Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology Experience in formal / static verification methodologies will be a plus Basic understanding of low power design techniques Good understanding of design components such as clock gates, level shifters, isolation cells and state retention cells. Experience with Synopsys NLP (native Low Power) tool. Experience with scripting languages such as Perl, Python is a plus Education Requirements BE/BTech/ME/MTech/MS Electrical Engineering and/or Electronics, VLSI from reputed university preferably with distinction

Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience inVerilog/System-Verilogis a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime isrequired. Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational Requirements: 2+ years of experience with abachelors/masters degree in Electrical engineering