378 Primetime Jobs - Page 5

As a Physical Design Engineer at HCLTech, you will be responsible for performing Timing analysis, timing convergence, SI/Noise analysis, and ensuring Signoff quality in the designs. With a minimum of 7 years of experience, you will demonstrate proficiency in handling multi-voltage scenarios design and STA closure on Low power designs. Your familiarity with industry standard EDA tools like Primetime will be essential for success in this role. Hands-on experience in Physical Design implementation will be a valuable asset. You will be expected to utilize your skills in scripting languages such as Perl and Tcl for automation purposes. Knowledge of 16/14/10/7/5nm nodes, along with an understanding of computer organization/architecture, will be advantageous. Your strong problem-solving abilities and attention to detail will be critical in this position. Effective communication skills and the ability to collaborate across diverse teams are essential qualities we are looking for in our ideal candidate. This challenging opportunity in Physical Design Engineering at HCLTech offers a platform to showcase your talents and contribute to cutting-edge projects. If you meet the above requirements and are excited about this opportunity, please send your resumes to maheswari.od@hcltech.com with the following details: CTC - ECTC - NP - Current Location - Preferred Location - Availability for F2F discussion on Saturday (9-Aug-2025) - Yes / No Join us at HCLTech and be part of our dynamic team working on full-chip timing and engineering projects. #EngineeringJobs #fullchiptiming,

You will be responsible for Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. It is essential to have expertise in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. Understanding Memory controller designs and microprocessors will be advantageous. Collaborating closely with SoC verification and validation teams for pre/post Silicon debug is a key aspect of this role. Your role will require hands-on experience in Low power SoC design, Multi Clock designs, and Asynchronous interfaces. Proficiency in using ASIC development tools such as Lint, CDC, Design compiler, and Primetime is necessary. An understanding of constraint development and timing closure will be a plus. Experience in Synthesis and knowledge of timing concepts will also be beneficial. Additionally, experience in creating padring and collaborating with the chip-level floorplan team is desirable. You must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 5+ years of relevant experience or a PhD with 4+ years of relevant experience will also be considered. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations will be provided upon request to support individuals with disabilities in the hiring process. The company expects all employees to adhere to relevant policies and procedures, including security protocols and confidentiality requirements. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not authorized to submit profiles, applications, or resumes through the Qualcomm Careers Site. For more information about this role, please reach out to Qualcomm Careers.,

As a Physical Design Engineer with 4+ years of experience, you will be responsible for Netlist2GDSII Implementation including Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, and Physical Verification. Your expertise should cover Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. Proficiency in programming languages like Tcl, Tk, and Perl is essential for this role. You should have hands-on experience with Synopsys and Cadence tools such as Innovus, ICC2, Primetime, PT-PX, and Calibre. Being well-versed in timing constraints, STA, and timing closure will be crucial for successful execution of projects. Your role will require inspirational leadership, effective communication skills, and the ability to collaborate in a global environment. Overall, your responsibilities will revolve around ensuring the successful implementation of physical design tasks, adhering to project timelines, and maintaining high quality standards throughout the process. Your contributions will play a key role in the development of cutting-edge semiconductor products.,

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ips for full chip timing analysis. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications Must have at least 8 years should be related to STA/Synthesis . Must have Involved in high Speed design tape-outs and constraint development across modes. Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrows systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ . Show more Show less

Qualcomm India Private Limited is seeking a candidate with a minimum of 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV. The ideal candidate should have experience in Logic design/micro-architecture/RTL coding, along with hands-on experience in designing and integrating complex multi clock domain blocks. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, clocking/reset/debug architecture are necessary. Experience in Multi Clock designs and Asynchronous interface is a must, as well as familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime. Collaboration with Design verification and validation teams for pre/post Silicon debug is expected, and hands-on experience in Low power design is preferable. Additionally, experience in Synthesis and understanding of timing concepts for ASIC is essential. The minimum qualifications for this position include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in the relevant fields with 2+ years of experience or a PhD with 1+ year of experience would also be considered. Qualcomm is an equal opportunity employer committed to providing accessibility to individuals with disabilities throughout the application/hiring process. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Employees are expected to adhere to all applicable policies and procedures, including security and confidentiality requirements. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not bear responsibility for any fees related to such submissions. For more information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is seeking a talented individual to join their Wireless IP team for the role of designing and developing cutting-edge RTL for next-generation cellular and Wi-Fi modem IPs used in mobile, wearable, and IoT platforms. In this role, you will be responsible for working on high-performance, low-power digital designs throughout the full VLSI development cycle, from architecture and micro-architecture to RTL implementation and SoC integration. You will have the opportunity to collaborate with global teams and contribute to market-leading wireless solutions. Your key responsibilities will include designing and implementing RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog, developing micro-architecture specifications, integrating complex subsystems into SoC environments, collaborating with various teams such as system architects, verification, SoC, software, DFT, and physical design teams, applying low-power design techniques, analyzing and optimizing for performance, area, and power, ensuring protocol compliance and performance of interconnects, conducting CDC and lint checks, and participating in post-silicon debug and bring-up activities. Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering experience, or - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering experience, or - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. - Minimum qualification of a Bachelors or Masters degree in Electronics, VLSI, Communications, or related field with proven experience in RTL design and SoC development. Preferred Skills & Experience: - 2-5 years of experience in digital front-end ASIC/RTL design. - Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. - Familiarity with wireless protocols such as IEEE 802.11, LTE, or 5G NR is highly desirable. - Solid understanding of bus protocols and bridge logic. - Experience with wireless modem IPs or similar high-performance digital blocks is a plus. - Familiarity with low-power design methodologies and CDC handling. - Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. - Exposure to post-silicon debug and SoC integration challenges. - Strong documentation and communication skills. - Self-motivated with a collaborative mindset and ability to work with minimal supervision. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations to individuals with disabilities during the application/hiring process. For more information about this role, please contact Qualcomm Careers.,

As an R&D Engineer at Synopsys, you play a crucial role in driving innovation in the field of physical design, with a focus on high-performance cores and IPs. Your deep understanding of physical design, coupled with your expertise in place & route, timing closure, and power optimization, enables you to tackle complex design challenges with ease. Your proficiency in low-power, high-performance design, particularly with advanced nodes under 5nm, sets you apart in the industry. Your responsibilities include developing and implementing innovative methodologies for high-performance cores and IPs, collaborating with a global team to enhance Performance, Power, and Area (PPA) metrics, and utilizing advanced technologies and tools to improve design quality and process efficiency. You will contribute to both flow development and the implementation of complex IPs, addressing critical design challenges using Synopsys implementation tools. Your impact as an R&D Engineer at Synopsys is significant, as you drive innovation in high-performance core and IP implementation methodologies, enhance the efficiency and predictability of the implementation process, and contribute to the development of cutting-edge semiconductor technologies. By solving complex design challenges and supporting the continuous advancement of Synopsys" technological capabilities, you play a key role in achieving best-in-class PPA and TAT targets. To excel in this role, you must possess deep knowledge of physical design, place & route, timing closure, and power optimization, along with experience in low-power, high-performance design and advanced nodes under 5nm. Proficiency in industry-leading tools like Fusion Compiler, Primetime, and Formality, as well as scripting languages such as TCL, Perl, and Python, is essential. A BS or MS in Electrical Engineering or a related field with 5+ years of relevant experience is required. Additionally, your self-motivation, strong investigative and problem-solving skills, enthusiasm for learning new technologies, and excellent communication skills in English are crucial attributes for success in this role. Joining the global team at Synopsys, you will contribute to the advancement of state-of-the-art high-performance cores and IPs implementation. Working with industry-leading tools and technologies, you will be part of a team focused on developing innovative methodologies to implement CPUs/GPUs and interface IPs efficiently. Your role will involve tackling complex design challenges, improving PPA metrics, and achieving best-in-class targets, thereby contributing to the continuous enhancement of Synopsys" technological capabilities.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 10-15 years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Education Requirements RequiredBachelor's, Electrical Engineering or equivalent experiencePreferredMaster's, Electrical Engineering or equivalent experience Keywords Innovus, FC, UPF, STA, Formal Verification, Genus, Primetime, Tempus, SOD Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po Preferred Qualifications Thorough knowledge of microprocessor architecture including expertise in one or more of the following areasinstruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams 4+ yrs exp in STA Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 7-14 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems "which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl /Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/ Masters degree in Electrical /Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational Requirements2+ years of experience with a Bachelors/ Masters degree in Electrical engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

You should possess a B.Tech/M.Tech degree in Electronics and Communication Engineering with 8 to 20 years of experience in physical design of semiconductor chips. The role is based in Hyderabad and follows a general shift schedule with no work from home option. Your responsibilities will include top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks such as timing and functional ECOs, SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. You must have prior experience working on 65nm or lower node designs, implementing advanced low-power techniques like Voltage Islands, Power Gating, and substrate-bias. In this role, you will provide technical guidance and mentorship to physical design engineers, interface with front-end ASIC teams to resolve issues, and focus on low-power design techniques including Voltage Islands, Power Gating, and Substrate-bias. You should have expertise in timing closure on DDR2/DDR3/PCIE interfaces, excellent communication skills, and a strong background in ASIC Physical Design encompassing Floor planning, Place & Route, extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Additionally, you should have extensive experience and detailed knowledge in physical design tools such as Cadence, Synopsys, or Magma, proficiency in scripting languages like PERL and TCL, and a strong skillset in Physical Verification. Familiarity with Static Timing Analysis using Primetime or Primetime-SI is required. Your written and oral communication skills should be excellent, with the ability to clearly document plans and effectively collaborate with cross-functional teams while prioritizing work based on project requirements.,

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verificationand sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Requirements : Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2. LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules and ESD rules has an added advantage Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development. Preferred qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Proven track record with multiple successful final production tape-outs Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks Be able to work under limited supervision and take complete accountability. Excellent written and verbal communication skills Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

Qualcomm India Private Limited is looking for a Hardware Engineer with over 12 years of experience in SoC design. You should have a strong understanding of AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. Knowledge of memory controller designs and microprocessors would be an added advantage. In this role, you will be responsible for constraint development and timing closure, working closely with SoC verification and validation teams for pre/post Silicon debug. Hands-on experience in Low power SoC design is required, along with expertise in Synthesis and understanding of timing concepts for ASIC. You should also have experience in Multi Clock designs and Asynchronous interface. Familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime is necessary. Minimum qualifications include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years of Hardware Engineering experience, or a Master's degree in the same field with 5+ years of experience, or a PhD with 4+ years of experience. If you are an individual with a disability and need accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. For reasonable accommodations, you may contact disability-accommodations@qualcomm.com. Qualcomm expects all employees to adhere to applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is for individuals seeking jobs at Qualcomm. Staffing agencies and individuals represented by agencies are not authorized to use this site. Unsolicited submissions from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers.,

You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and DFY, and Tapeout. You should have expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep submicron processes, along with an understanding of process variation effects. Experience in variations analysis/modeling techniques and convergence mechanisms would be a plus. Proficiency in Synopsys ICC2 and PrimeTime physical design tools is essential for this role. Additionally, skill and experience in scripting using Tcl or Perl are highly desirable. Qualifications required for this position include a BE/BTech or ME/MTech degree with a specialization in the VLSI domain. The ideal candidate should have 5-10 years of relevant experience in the field.,

We are seeking a highly experienced Senior Physical Design Engineer with 8+ years of experience in block-level and full-chip physical implementation. The candidate should be proficient in physical design flows and methodologies for advanced technology nodes. Key Responsibilities: Drive physical implementation from RTL to GDSII (floorplanning, placement, CTS, routing) Perform timing analysis, congestion analysis, and physical verification (DRC/LVS) Optimize for performance, power, and area (PPA) Collaborate closely with RTL, STA, DFT, and package teams Own signoff checks (IR drop, EM, Antenna, Crosstalk, etc.) Support tape-out and silicon validation activities Requirements: 8+ years of experience in physical design implementation and signoff Strong hands-on experience with tools like ICC2, Innovus, Primetime, RedHawk, Calibre Solid understanding of timing closure, IR/EM analysis, and power optimization Experience with advanced nodes (7nm, 5nm, etc.) is a plus Good scripting skills (TCL, Perl, Python) for automation Strong communication and teamwork skills

Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Master's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure.

As a Senior Physical Design Engineer, you will be responsible for leading the Netlist-to-GDSII implementation process on advanced submicron technology nodes. Your expertise in utilizing industry-standard EDA tools and your understanding of timing closure and physical verification will be crucial for this role. Your key responsibilities will include driving the entire Netlist-to-GDSII flow, which involves tasks such as floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. You will also be required to conduct Static Timing Analysis (STA) to ensure timing closure across all design corners, as well as execute power integrity and physical verification checks (LVS, DRC). Collaboration with cross-functional teams including RTL, STA, packaging, and DFT will be essential to successfully handle complex designs on 28nm and below technology nodes. To excel in this role, you must possess strong hands-on experience with tools such as Synopsys/Cadence Innovus, ICC2, Primetime, PT-PX, and Calibre, along with a solid understanding of Physical Design Methodologies including Floorplanning, Placement, CTS, Routing, and STA. Proficiency in timing constraints and closure, Tcl/Tk/Perl scripting, and working with submicron nodes (28nm and below) are also essential skills required for this position. While not mandatory, familiarity with Fusion Compiler, a broader understanding of signal and power integrity, as well as experience in workflow automation and tool scripting would be considered advantageous for this role. If you are excited about the prospect of taking on this challenging and rewarding opportunity, we encourage you to submit your resume to hemanth@neualto.com or spoorthy@neualto.com to express your interest.,

As a VLSI Mentor / Guest Faculty specializing in Advanced Digital Systems & Low Power Design at Spandsons Horizon Engineering, you play a crucial role in guiding 5th, 6th, and 7th-semester B.E./B.Tech students in advanced VLSI concepts and practical applications. This contract role, based in Salem, offers a unique opportunity to directly influence the academic and career growth of 60 aspiring engineers. Your key responsibilities include delivering engaging sessions covering topics such as Advanced Digital System Design with Verilog HDL and Low Power VLSI Design. You will also provide hands-on guidance for lab assignments and projects using various tools like Xilinx Vivado, ModelSim, LTspice, and more. Facilitating interactive learning and ensuring alignment with the semester curriculum are essential aspects of this role. To qualify for this position, you need a minimum of 4-5 years of industry experience in VLSI design, proficiency in relevant EDA tools and hardware platforms, excellent communication skills, and a passion for teaching and mentoring. The program details include a total of approximately 60 students, with sessions scheduled on Thursdays and Fridays for 12 hours per week starting on July 24th & 25th. The program will run for Semesters 5, 6, and 7. In addition to a comprehensive program, benefits such as accommodation, food, and the opportunity to impact the next generation of VLSI engineers are provided. Join us at Spandsons Horizon Engineering and be part of a forward-thinking academic institution.,

As STA engineer , the role would expect the candidate to have deployment of new features and or methodologies related to STA and ECO domain . Scope of the work would cover (but not limited to) STA flow/methodology development, continuous efficiency improvement, Flow development/Support for ECO convergence with tools in STA and ECO domain (PrimeTime, Tempus, Tweaker, PrimeClosure to name a few). There would be challenges for timing convergence at both block and Top level on cutting edge technology on high performance designs would have to be resolved for ensuring successful design tapeouts on time with high quality. Basic Hands-on on Scripting is a must to have for candidate. Specific skills & knowledge Bachelor or Master in Electronics Engineering and specialization in VLSI domain. 5-8 years of hands-on experience in SoC and IP level objectives on low geometry nodes (5/14/16/28/40nm). Experience in Synopsys Cadence tools, low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project Proven experience in delivering timing closure methodology of mixed signal SoC with high speed PHYs, IOs, PMU IP etc. closing analog / digital interfaces timing & signal integrity issues Experience in customizing flows & methodology to meet low power & area objectives of SoC and leading team to execute on time Ability to use scripting languages / automation of Physical Implementation methodology creation and deployment Should have proven experience in demonstrating strong technical leadership to deliver on commitment, anticipation of challenges, assertive communication and excellent team player. Excellent communication skills with proven experience in international relationships