573 Primetime Jobs - Page 7

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are looking for a passionate & experienced EDA Methodology Engineer to join our timing team focusing on timing methodology using IBM Einstimer, Cadence & Synopsys...

Location: Bangalore, Hyderabad, Noida, and Coimbatore. Skills: Soc level floorplanning, partitioning, timing budget generations, power planning, SOC PnR, CTS, block integration Handling timing closure of high frequency blocks. Expertise in signoff closure Timing with SI and OCV, Power, IR and physical verification at both block and chip level. Understanding constraints and fixing techniques. Experience in physical verification Understanding SI prevention, fixing methodology and implementation. Proficient in Synopsys ICC or Cadence or Mentor Olympus and Atoptech tool set. Experience in Design Automation and UNIX system. Experience in Tcl/ PERL is a plus. Primary Skills: Able to handle Soc PNR...

You have 24 years of experience in ASIC Physical Design and Timing Analysis. Your hands-on expertise includes working with tools such as: - Physical Design: Innovus, ICC2, Fusion Compiler, or similar - STA: PrimeTime, Tempus - Physical Verification: Calibre, Pegasus Open positions available: - PD- 2-4 years (Chennai) - STA - Top level or Fullchip - 4+ years (Bangalore/Pune/Hyderabad) You should have an immediate to 30 days notice period.,

Role Overview: You have 12+ years of experience in Digital ASIC/Processor Design with strong fundamentals in core areas such as Microarchitecture, Computer Arithmetic, Circuit Design, and Process Technology. Your communication skills are excellent, enabling you to collaborate effectively with design teams globally. Key Responsibilities: - Lead, train, and mentor a team of junior engineers for a large modem design project in advanced process nodes - Collaborate with RTL, DFT, and PD leads to take a project from Post-RTL to Netlist release, focusing on area, timing, power, and testability - Write timing constraints, conduct synthesis, formal verification, CLP, Primetime, PTPX, and CECO tasks -...

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco''s silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integr...

Role : Senior STA Engineer Experience Required : 4-5 YEARS Job Location: HYDERABAD Bachelors or Masters degree in Electrical/Electronics Engineering. Preferred Qualifications: Experience with full-chip STA closure. Exposure to low-power design techniques and multi-mode/multi-corner analysis. Knowledge of timing integration for third-party IPs. Required Skills: Strong understanding of STA fundamentals and timing closure methodologies. Proficiency in tools like PrimeTime, Tempus, Tweaker, Timevision, Fishtail. Experience with scripting languages (TCL, Perl, Python) for automation. Familiarity with advanced nodes (e.g., 7nm, 5nm, FinFET). Good grasp of physical design flow and constraints manag...

Responsible for leading Physical Design and Timing Closure of low power SoCs. Responsible to achieve die area, performance, power goals for hierarchical blocks and top. Drive physical design implementation which includes package co-design , floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve design, methodology and process aspects. Enable next generation of place and route engineers via mentoring and thought leadership. Your Profile You are best equipped for this task if you have: Hands-on experience in physica...

You have a rewarding opportunity at Qualcomm India Private Limited in the Engineering Group, specifically in the Hardware Engineering team. As a Senior SoC Design Engineer, you will play a crucial role with your extensive experience in SoC design and expertise in various protocols and architectures. Let's delve deeper into the responsibilities and qualifications required for this role: **Role Overview:** - Utilize your 15+ years of experience in SoC design to contribute effectively to the team - Demonstrate proficiency in AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking/reset/debug architecture - Showcase your knowledge of peripherals like USB, PCIE, and SDCC - Gain an under...

As an engineer at Qualcomm India Private Limited, you will have the opportunity to work on cutting-edge Wireless Technology projects, specifically focusing on IEEE 802.11 standards. Your role will involve collaborating with design teams globally and contributing to the development and implementation of hardware blocks for complex SoCs. You will also play a critical part in the WLAN subsystem, ensuring the successful delivery of IPs to the SOC design team. Strong fundamentals in Microarchitecture, Computer Arithmetic, Circuit Design, and Process Technology will be essential for excelling in this role. Key Responsibilities: - Develop HW blocks (IP design) and conduct High/Mid/Low level Design ...

We are looking for a skilled professional with 5-15 years of experience to join our team as an SCOM in IDESLABS PRIVATE LIMITED, located in [location to be specified]. The ideal candidate will have a strong background in recruitment services and excellent communication skills. Roles and Responsibility Manage and coordinate recruitment activities to meet client requirements. Develop and implement effective recruitment strategies to attract top talent. Build and maintain relationships with clients and candidates for successful placements. Conduct interviews and assessments to identify the best candidates. Collaborate with internal teams to ensure seamless recruitment processes. Analyze recruit...

We are looking for a skilled SAP DRC Engineer with 7 to 12 years of experience. The ideal candidate will have expertise in the SAP DRC module and BTP of SAP, SD, FI, E-Doc Cockpit, and project management skills. This position is available in PAN India, including Bangalore, Hyderabad, Chennai, Noida, Pune, and Gurgaon. Roles and Responsibility Design and implement SAP DRC solutions to meet business requirements. Collaborate with cross-functional teams to ensure seamless integration of SAP DRC with other modules. Develop and maintain documentation for SAP DRC projects. Provide training and support to end-users on SAP DRC functionality. Troubleshoot and resolve technical issues related to SAP D...

We are looking for a skilled professional with 7 to 15 years of experience in the field of Physical Design to join our team. The ideal candidate will have a strong background in Floor Planning, Innovus, Fusion Compiler, and programming skills in Tcl/Tk/Perl. Roles and Responsibility Develop and implement physical design methodologies for submicron technology nodes. Utilize expertise in Floor Planning, Innovus, and Fusion Compiler to optimize design performance. Collaborate with cross-functional teams to ensure seamless integration of physical design with other components. Apply knowledge of physical design principles and methodologies to improve design quality. Troubleshoot and debug complex...

Key Responsibilities: Drive block-level and/or full-chip physical design from RTL to GDSII. Floorplanning, placement, clock tree synthesis (CTS), and routing. Work on static timing analysis (STA) and timing closure. Run and debug physical verification (LVS/DRC/ERC) and power integrity checks (IR Drop/EM). Collaborate with RTL, DFT, synthesis, verification, and packaging teams. Ownership of PPA (Power, Performance, Area) targets and meeting timing goals. Participate in multiple tape-outs and manage block-level signoff closure. Automate and optimize flows using Tcl, Perl, Python, or shell scripting. Keep up-to-date with the latest EDA tools and technology trends. Required Skills & Experience: ...

Role & responsibilities: The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc . The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc. Preferred candidate profile : • 4-7 years of experience in ASIC Physical Design. • Have good knowledge of entire physical design process from floorplan till GDSgeneration. • Good Exposure to Physical Verification Process. • Have hands-on experience in latest sub-micron technologies below 10 nm • H...

Responsibilities: Collaborate with cross-functional teams on project deliverables. Optimize timing closure through innovative techniques. Perform physical verification using Synopsys tools.

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and dedicated R&D Engineer with a deep understanding of physical design and a knack for solving complex design challenges. With a strong background in place & route, timing closure, and power optimization, you thrive in dynamic environments where technological...

Responsibilities In this role, you will be responsible for Timing methodology definition and closure of designs using industry standard tools for chiplet designs for custom and domain specific products. The chiplets will be leveraged to enable modular design and support multiple products. As part of this team, the candidate will work with leading edge technologies and solutions across multiple domains including SoC multi-die implementations (2.5 and 3D), power delivery, leading edge memory technologies, innovate thermal solutions, on die clocking, and fabrics. The team will also look at options to enhance product power/performance/area/cost thru improved tools and methodologies. The successf...

STA Engineer Job Title: STA (Static Timing Analysis) Engineer Experience: 2-5 years Education: B.Tech/M.Tech in ECE Responsibilities: Perform timing analysis and closure using Prime Time or Tempus Work with RTL, synthesis, and PnR teams to fix timing issues Define and debug timing constraints (SDC) Analyse timing corners, ECOs, and sign-off checks Requirements: Strong understanding of timing concepts (setup, hold, skew, etc.) Experience with timing tools and constraints debugging Familiar with multi-voltage/multi-mode designs

Responsible for high-performance microprocessor blocks RTL to GDSII implementation Perform block-level synthesis, floor-planning, placement, and routing. Close the design to meet timing, power budget, and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8-12 years of industry experience in physical design methodology. Good knowledge and hands-on experience in physical design methodology, which includes logic synthesis, placement, clock tree synthesis, and routing. Should be knowledgeable ...

The Team: Commodity Insights Research & Analytics Solutions seeks a principal analyst / Senior analyst for power and renewable market research for South Asian countries. The South Asia Power and Renewable Research group operates within the broader APAC research team, which is part of the Global Power team under Research & Analytics Solutions. The team provides forward-looking market analysis and delivers actionable insights to clients through written reports, presentations, and direct engagement with clients. Responsibilities and Impact: this position supports the new and existing research & analysis, and market modelling activities. He/she will be responsible to produce accurate, timely, an...

About The Role Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. ? Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product de...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...