574 Primetime Jobs - Page 11

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

We are looking for a Senior Manager Silicon Design Engineering to lead a team of talented engineers in developing NPU IP. This IP goes to several products including client and embedded products and serves as AI inference accelerator. This role requires deep understanding of design implementation and flows, tools and methodologies. THE PERSON : The ideal candidate should have demonstrated experience in leading front-end design and integration of sub-systems for complex SOCs. The candidate must be able to communicate effectively and work optimally with different teams across AMD.The candidate must have excellent analytical and problem-solving skills. KEY RESPONISIBILITES : Manage design and fr...

As a Principal Physical Design Engineer at our company, you will play a crucial role in leading a Physical Design team specializing in Low Power Design. Your responsibilities will encompass a wide range of tasks, from performing power analysis at different design stages to developing innovative power optimization techniques. You will be expected to lead and mentor a team, collaborate with cross-functional teams, manage external vendors, and stay updated on the latest advancements in the industry. Your expertise in RTL2GDSII design flow, power analysis and reduction using tools like PrimeTime PX/PrimePower, scripting languages such as TCL and Python, RTL design, and power optimization tools l...

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

Requirements :Bachelors or Masters Degree with a strong VLSI BackgroundMinimum 3 years of experience in the area of Synthesis Synthesis Engineer: (3-10 Years)Key Responsibilities:Synthesis Environment setupValidating synthesis SDC qualityUtilize Synthesis tool variables and methodologies to extract the best area/power achievable for the process node Checking the synthesis DEF qualityAnalyze critical timing violation groups and congestion solve them by finetune floorplan or placement constraints Compare area/power with previous projects and check current project results DFT Insertion and debugging basic DFT issues Discuss directly with Design teams & Physical design teams to get the best synt...

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills:

Education : BTech in ECE/EEE or MTech VLSI No. of positions : 5 Desired Skills: Minimum 3+ year of experience Should have block/SOC level netlist-gds2 experience. Expertise in Floor planning, Power planning, CTS. Should be capable of handling block-level timing closure. Good scripting skills (TCL/Perl/Shell). Experience on low power implementation techniques is preferred. Synopsys/Cadence tool experience is preferred. Should be a team player and perform lead role where ever required. Good communication analytical skills.

ofAbout the Job 3 to 8 years of relevant experience Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and pref...

Strong understanding of timing closure for multi-clock, high-frequency timing, congestion, crosstalk, and area-sensitive designs. Collaborate with RTL designers for constraint development and cleanup. Proficient in Synopsys/Cadence tools with hands-on experience in advance features of Design compiler and PrimeTime SI. Deep expertise in low-power design (UPF/CPF), clock gating, logic optimization, and integration of high-speed interfaces like DDR and PCIe Provide technical leadership to successful tape outs at advanced technology nodes (7nm, 5nm and 3nm). Good scripting, communication and debugging skills.

Wipro Limited is a leading technology services and consulting company dedicated to creating innovative solutions that cater to the most complex digital transformation requirements of clients. With a global presence spanning 65 countries and a workforce of over 230,000 employees and business partners, Wipro is committed to helping customers, colleagues, and communities thrive in an ever-evolving world. For more information, please visit www.wipro.com. As a Physical Design Lead, you will be based in Bangalore, Hyderabad, or Pune with a minimum of 8 years of experience. Your responsibilities will include handling Netlist2GDSII Implementation tasks such as Floor planning, Placement, CTS, Routing...

Qualcomm India Private Limited is a leading technology innovator that aims to create a smarter, connected future for all by pushing the boundaries of what's possible and driving digital transformation. As a Qualcomm Hardware Engineer within the Engineering Group, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To qualify for this ...

Alternate Job Titles: Senior R&D Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and driven engineering professional with a strong foundation in VLSI concepts, CMOS circuit design, and EDA tools. With2-3 years of hands-on experience in the semiconductor industry, you thrive in dynamic environments ...

Are you ready for a career that presents challenges while also instilling a sense of pride in your work At Ambit, we provide an ideal platform for individuals to work and advance in the field of semiconductor design. Our employees enjoy the freedom to work in their own adaptable ways, with the necessary support to continue learning and improving their skills. We firmly believe that in order for a company to achieve significant growth through innovation, its employees must be empowered to experiment and innovate freely. The positive and vibrant work environment at Ambit reflects our management's dedication to our employees and their values. Join us today for a promising future in semiconducto...

ACL Digital is searching for a skilled and experienced Static Timing Analysis (STA) Engineer to become a part of the growing VLSI team. If you possess expertise in timing analysis and have previously handled full-chip designs, we are interested in hearing from you. As an STA Engineer at ACL Digital, your responsibilities will include driving full-chip STA from RTL to GDSII, developing and verifying timing constraints (SDC) for intricate SoCs, conducting timing closure and sign-off utilizing tools such as PrimeTime, collaborating with RTL, physical design, and DFT teams for ECOs and timing fixes, as well as analyzing timing reports, debugging violations, and suggesting optimization strategies...

Job Description Key Responsibilities: Timing Analysis & Closur e Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. Achieve timing closure by resolving violations and optimizing paths. Constraint Development Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths). Integrate constraints from multiple IPs for hierarchical STA. Tool Usage & Flow Integration Use STA tools like Synopsys PrimeTime, Cadence Tempus , or equivalent. Integrate STA into the overall design flow and automate processes for efficiency. Job Description: Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, an...

About Astound Digital At Astound Digital, we are pioneers in the digital landscape, dedicated to transforming how the world interacts with technology, data, and creativity Our role as trusted advisors in the digital landscape empowers the worlds most innovative brands with frictionless, end-to-end customer experiences We are known for our comprehensive solutions, proven expertise, and collaborative, nimble approach that instills confidence in our clients Join us to navigate and lead in the ever-changing digital world, where your impact will extend beyond the ordinary, Job Purpose The QA Engineer will be part of a high-performance feature-driven QA team responsible for building and testing co...

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills:

Education : BTech in ECE/EEE or MTech VLSI No. of positions : 5 Desired Skills: Minimum 3+ year of experience Should have block/SOC level netlist-gds2 experience. Expertise in Floor planning, Power planning, CTS. Should be capable of handling block-level timing closure. Good scripting skills (TCL/Perl/Shell). Experience on low power implementation techniques is preferred. Synopsys/Cadence tool experience is preferred. Should be a team player and perform lead role where ever required. Good communication analytical skills.

Key Skills: Static Timing Analysis,PrimeTime Roles and Responsibilities: Conduct block-level and full-chip static timing analysis across all phases of development. Develop timing methodologies and infrastructure from RTL synthesis to timing closure. Collaborate with architects and designers to define block and chip-level timing constraints. Define analysis scenarios and margin strategies with system and technology teams. Establish comprehensive signoff methodology for robust silicon delivery. Partner with physical design teams for timing closure and design sign-off. Create ASIC timing constraints and drive closure using industry-standard tools. Address deep-submicron STA challenges including...

As a Principal Physical Design Engineer at our company, you will play a crucial role in leading a Physical Design team with a focus on Low Power Design. Your expertise in Low Power Design will be utilized as you take the lead in various aspects of the physical design skill set. You will be based in either Hyderabad or Bangalore and will be required to work onsite for 5 days a week. Your responsibilities will include performing comprehensive power analysis from RTL to GDS, contributing to the development and automation of power analysis flows, identifying power inefficiencies, and providing feedback to RTL design. You will be responsible for developing power optimization recipes from RTL to G...

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work, to amplify human imagination and intelligence. Make the choice to join us today. NVIDIA is an equal opportunity employer. We are now looking for a DFT Verification Engineer. Design-for-Test (DFT) Engineering at NVIDIA ...

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL de...

Job Description: Strong understanding of Physical Design with hands-on experience in RTL2GDS flow. Ability to close tiles/blocks including timing, noise, power, IR, phyV, conformal equivalence, and signoff checks. Exposure to advanced technology nodes (7nm and below) and related design challenges. Experience with the Synopsys tool suite is required. Knowledge of high-frequency design (>2GHz)

Role & responsibilities Leading a team of 3-5 engineers for block-level implementation. Collaborating with a cross-functional team for project planning and completion. Contribute to enhancement of methodologies and flow. Overseeing timing closure, power optimization, and physical verification using industry-standard EDA tools. Managing resources and schedules to ensure timely and quality deliverables. Technical leadership to analyze and debug complex issues and recommend. Supporting and developing best practices in design methodology, quality assurance, and continuous process improvement Preferred candidate profile Experience of Netlist-to-GDS design flow, including floor-planning, placement...

We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team. Key Responsibilities Work closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPs Carry out floor planning, and physically aware synthesis on high-performance IPs Perform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL team Leads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions...