Power Integrity ( Senor Staff Engineer )

Senor Staff Engineer - Power Integrity / IR drop analysisThe PI Signoff / IR Drop Analysis Lead is responsible for Signoff level IR drop, Power/Signal EM analysis of a Subsystem and Full SoC. He is responsible for running EM and Static/Dynamic IR analysis for various modes/power scenarios, root cause failures, provide fixing solutions. He should follow/define best practices and strategy as per technology node. He contributes to problem solving related to overall PI analysis.Responsibilities include EM and IR drop analysis (vector and vectorless) for both block and full chip designs for various power modes and scenarios. Provide feedback / improvement / fixing suggestions to various stake holders like owners for Power, package, pattern, physical design, timing, etcAnalyze weakness area(s) in the design and provide fixing solutions.Automation for reporting, debug, fixing suggestions/ECOs.Setting up and Maintaining the environment for the overall PI analysisProvide training to junior folks in the team to enhance their productivity and to extract quality work

The Candidate Must Have:

8+ years of experience in EM and IR analysis with exposure to Physical Design and timing analysisHands-on experience on RedHawk-SC or Voltus, preferably bothHands-on experience on Low power, multi voltage, power off (MTCMOS), and mixed signal designsExperience in leading block level or chip level IR/EM analysisAbility to debug and resolve issues with inputs like – design data, library info, package, bump locations/RDL routingAutomation skills in TCL/Perl/awk/Python/Unix shellTeam player who is able to autonomously plan and perform tasksExperience to Lead a team of 3-4 folks, by prioritizing and assigning tasks, guide and mentor juniors on the jobWorked on technologies 16nm and below, preferably on N7 and lower nodesExposure on designing power mesh especially on low power, power shut off designsSome exposure to Physical Design and timing analysis tools like (Innovus, Tempus, ICCompiler2, PrimeTime)

Requirement

The Candidate Must Have:

8+ years of experience in EM and IR analysis with exposure to Physical Design and timing analysisHands-on experience on RedHawk-SC or Voltus, preferably bothHands-on experience on Low power, multi voltage, power off (MTCMOS), and mixed signal designsExperience in leading block level or chip level IR/EM analysisAbility to debug and resolve issues with inputs like – design data, library info, package, bump locations/RDL routingAutomation skills in TCL/Perl/awk/Python/Unix shellTeam player who is able to autonomously plan and perform tasksExperience to Lead a team of 3-4 folks, by prioritizing and assigning tasks, guide and mentor juniors on the jobWorked on technologies 16nm and below, preferably on N7 and lower nodesExposure on designing power mesh especially on low power, power shut off designsSome exposure to Physical Design and timing analysis tools like (Innovus, Tempus, ICCompiler2, PrimeTime)