Posted:1 week ago| Platform:
Work from Office
Full Time
**Job Summary:** We are looking for an experienced and results-driven IC Physical Design Engineer with 5+ years of hands-on experience in digital backend implementation of complex SoCs or ASICs. In this role, you will lead or contribute significantly to block-level and full-chip physical design, timing closure, and sign-off processes in advanced technology nodes. You will work cross-functionally with RTL, DFT, verification, and packaging teams to deliver high-quality silicon on aggressive schedules. **Key Responsibilities:** + Lead physical implementation of blocks and/or full chip through all stages: floorplanning, power planning, placement, CTS, routing, and sign-off. + Drive timing closure using static timing analysis (STA) and optimization techniques for PPA (Power, Performance, Area). + Own physical verification (LVS, DRC, Antenna, ERC) and ECO implementation. + Perform IR/EM analysis, noise checks, and low power verification (UPF/CPF-based). + Interface with RTL, DFT, and verification teams to resolve cross-functional issues and ensure successful tape-out. + Guide junior engineers and review their work to maintain high quality and consistency. + Develop automation scripts to streamline physical design tasks using TCL, Python, or Perl. Collaborate with CAD/Methodology teams to enhance \#LI-RT1 **More details about our company benefits can be found here:** https: / / www.onsemi.com / careers / career-benefits We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.
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