Physical Design Engineer, Block Owner

Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms.

In this hybrid role, you will report to an ASIC Design Manager

This position will require the ability to work some hours that align with the team in the Pacific Daylight Time (PDT) zone on an as needed basis.

You will:

• Participate in the Physical Design of advanced silicon for our self-driving cars.
• Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS with a focus on block ownership.
• Collaborate with internal logic and internal and external PD teams to achieve the best PPA possible. This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL.

You have:

• 5+ years of experience on PD design tasks in advanced silicon nodes with a minimum of 2 tapeouts.
• Expertise in owning a complex, computation heavy, high frequency block from RTL-to-GDS with a focus on Synthesis and Placement but knowledge and experience with all tasks.
• Deep knowledge of timing constraints with a demonstrated ability to generate, maintain, and verify SDC files.
• Proficient in scripting with demonstrated facility in TCL and Python.
• Excellent verbal and written communication skills and demonstrated capability to work under tight schedule.

We prefer:

• Experience with CTS and an understanding of routing for both CTS and general timing closure.
• Experience working with external partners on PD closure.
• Understanding of DFT, especially MBIST.
• Understanding of different memory types and their tradeoffs and experience with custom and structured memories.
• Deep understanding of performance, power and area (PPA) tradeoffs.
• Strong experience with back end flows (PI/SI, DRC/LVS, etc).

May require infrequent travel to Mountain View, CA or to partner sites (Up to 15%)