Posted:19 hours ago|
Platform:
On-site
Full Time
? Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL/DFT tools
? Extensive experience in Back-end design
? Experience on Mentor Graphics EDA flow is an added advantage
? Responsible for development and support of Projects.
? Responsible for Debugging the source codes in Verilog, SV, and UVM.
? Responsible for Training Delivery and Support
? Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design
? 3 to 8 years industry/teaching experience
? Good communication & presentation skill
Best NanoTech
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