4 Dft Tools Jobs

You will be part of the Strategic Silicon Solutions (S3) Business Unit at AMD, contributing to the realization of customers" special requirements for designs across a wide range of products. Your role as a DFT (Design for Testability) Lead involves implementing and managing DFT methodologies to ensure the quality and reliability of the products developed by the team. Your responsibilities will include leading the design and implementation of advanced DFT architectures and methodologies, collaborating with various teams to integrate DFT features seamlessly, developing and optimizing test plans for silicon validation, driving the adoption of cutting-edge DFT tools and techniques, providing guidance and mentorship to junior engineers, analyzing test data to identify and resolve issues promptly, ensuring compliance with industry standards and best practices, and staying updated with the latest advancements in DFT technology to enhance ongoing projects. To excel in this role, you should possess extensive knowledge of DFT techniques such as scan insertion, BIST, JTAG, and boundary scan, proficiency in DFT tools like Mentor Graphics Tessent, Synopsys DFTMAX, and Cadence Encounter Test, a strong grasp of DFX design and verification processes, excellent problem-solving and analytical abilities, exceptional leadership and team management skills, and effective written and verbal communication capabilities. Ideally, you should hold a Bachelor's or Master's degree in a related discipline and have at least 15 years of experience in the field. By joining AMD, you will have the opportunity to work on cutting-edge technologies and be part of a dynamic team dedicated to pushing the boundaries of innovation in the semiconductor industry.,

As a member of the Strategic Silicon Solutions (S3) Business Unit within AMD, your execution will help bring to life customers Special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more. We are seeking a highly experienced and motivated DFT (Design for Testability) Lead to join our dynamic team, with a strong background in implementing and managing DFT methodologies. The DFT Lead will be responsible for leading a team of engineers to develop and execute DFT strategies that ensure the highest level of product quality and reliability. Responsibilities Lead the design and implementation of advanced DFT architectures and methodologies. Collaborate with cross-functional teams including design, verification, and manufacturing to ensure seamless integration of DFT features. Develop and optimize test plans for various stages of silicon validation. Drive the adoption of state-of-the-art DFT tools and techniques to improve test coverage and efficiency. Provide technical guidance and mentorship to junior DFT engineers. Analyze test data to identify and resolve issues in a timely manner. Ensure compliance with industry standards and best practices for DFT. Stay updated with the latest advancements in DFT technology and integrate relevant innovations into current projects. Qualifications Extensive knowledge of DFT techniques including scan insertion, BIST, JTAG, and boundary scan. Proficiency in DFT tools such as Mentor Graphics Tessent, Synopsys DFTMAX, and Cadence Encounter Test. Strong understanding of DFX design and verification processes. Excellent problem-solving and analytical skills. Exceptional leadership and team management abilities. Effective communication skills, both written and verbal. ACADEMIC CREDENTIALS: Bachelor s or Master s degree in related discipline preferred with 15+Yrs of exp

MTS SILICON DESIGN ENGINEER ? Job Title: Member of Technical Staff (MTS) SoC Scan and ATPG Experience: 6+ Location: Bangalore Job Description: We are looking for a talented Member of Technical Staff (MTS) with expertise in SoC Scan, Automatic Test Pattern Generation (ATPG), pattern retargeting, and simulations. The ideal candidate will play a crucial role in developing and verifying robust DFT solutions to ensure the quality and testability of our cutting-edge SoC designs. Key Responsibilities: Develop and execute SoC Scan insertion strategies and ensure integration across various modules. Generate and validate ATPG patterns to achieve high fault coverage for SoC designs. Perform pattern retargeting and conduct thorough simulations to ensure test reliability and efficiency. Debug and resolve test coverage gaps or failures during pattern simulations and silicon testing. Collaborate with cross-functional teams to ensure seamless DFT implementation and validation processes. Optimize test methodologies to improve yield and reduce test time. Required Skills: Strong hands-on experience in SoC Scan implementation and ATPG pattern generation. Proficiency in pattern retargeting and running simulations to ensure high-quality results. Familiarity with industry-standard DFT tools like Mentor Tessent, Synopsys TetraMAX, or Cadence Modus. Solid understanding of RTL design, verification, and debugging. Expertise in scripting languages (e.g., Python, TCL, Perl) for test process automation. Problem-solving skills for silicon debug and test failure analysis. Preferred Qualifications: Experience with low-power ATPG techniques and fault diagnostics. Knowledge of advanced DFT features such as compression and hierarchical ATPG. Exposure to post-silicon validation and production test flows. Education: Bachelor's/Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related field.

Sr DFT Engineers and Managers - location remote any where in India Job Summary Our clients Arasan Chip Systems (www.arasan.com) based in US are seeking for their India Development Center Senior and Experienced DFT Engineer with 68 years of hands-on expertise in Design-for-Test methodologies and implementation for complex SoC designs. The candidate will be responsible for developing and integrating DFT architectures, driving ATPG and MBIST flows, and working closely with RTL design, physical design, and test teams to ensure high test coverage and silicon readiness. Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan (JTAG), and test points. Develop and run ATPG and MBIST for various memory instances. Generate and validate test patterns (stuck-at, transition, path delay). Collaborate with RTL, synthesis, and physical design teams to ensure DFT integration and timing closure. Participate in silicon bring-up and ATE support. Support internal reviews, audits, and DFT documentation. Skills Strong experience with industry-standard DFT tools (Mentor Tessent, Synopsys DFTMAX, Cadence Modus, etc.). Hands-on experience in scan insertion, ATPG, MBIST, boundary scan, and test compression techniques. Familiarity with ATE pattern generation and silicon debug flows. Solid understanding of RTL/gate-level simulation, synthesis, STA, and timing-aware DFT flows. Proficiency in scripting languages (TCL, Perl, Python) for automation. Excellent analytical and problem-solving skills. Qualifications B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related field. 6–8 years of relevant experience in DFT for ASIC/SoC design. Preferred Exposure to low-power DFT methodologies (UPF/CPF flows). Prior experience with automotive or high-speed PHY IP integration is a plus. Knowledge of IEEE standards (1149.1, 1500, 1687).