9 Dft Tools Jobs

Designation: Member Technical Staff Location : Bangalore Experience : 3-9 Years Education : B.E. or B.Tech or MTech VLSI / ECE/EEE Industry Type : Education / E-Learning / Semiconductor Functional Area : Training Job Description ? Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL/DFT tools ? Extensive experience in Back-end design ? Experience on Mentor Graphics EDA flow is an added advantage ? Responsible for development and support of Projects. ? Responsible for Debugging the source codes in Verilog, SV, and UVM. ? Responsible for Training Delivery and Support Desired Candidate Profile ? Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end d...

About Us Tessolve offers a comprehensive suite of pre- and post-silicon solutions, delivering complete turnkey services from design to packaged parts. Founded in Bangalore, India, the company has expanded its presence to over 12 countries and serves 9 of the top 10 tech companies globally. With advanced silicon and system testing labs, Tessolve provides clients with a one-stop shop for both hardware and software needs, enabling faster market entry with its range of complementary solutions. For more details, visit www.tessolve.com. Key Responsibilities Develop and implement DFT architectures for complex SoC/ASIC designs. Own and execute DFT insertion, ATPG pattern generation, and fault gradin...

Job Requirements We are seeking a Senior DFT Engineer with 3-5 years of experience in Design for Test (DFT). The ideal candidate must have a BTech degree and be located in Ahmedabad. Key Responsibilities Develop and implement DFT methodologies for complex integrated circuits Collaborate with design and verification teams to ensure successful DFT implementation Perform scan insertion, ATPG, and memory BIST Conduct DFT simulations and debug DFT issues Qualifications Bachelor's degree in Engineering (BTech mandatory) 3-5 years of experience in DFT Proficiency in industry-standard DFT tools and methodologies Strong problem-solving skills and attention to detail If you meet the requirements and a...

THE ROLE: We are seeking a highly experienced DFT (Design for Test) Principal MTS to join our CPU Cores team in Bangalore. The ideal candidate will have a strong technical background and extensive experience in DFT methodologies, particularly in the context of CPU core design and development. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Lead DFT Strategy and Implementation Develo...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com. Basic Qualifications Strong academic and technical background in electrical engineering. A Bachelor's de...

You will be part of the Strategic Silicon Solutions (S3) Business Unit at AMD, contributing to the realization of customers" special requirements for designs across a wide range of products. Your role as a DFT (Design for Testability) Lead involves implementing and managing DFT methodologies to ensure the quality and reliability of the products developed by the team. Your responsibilities will include leading the design and implementation of advanced DFT architectures and methodologies, collaborating with various teams to integrate DFT features seamlessly, developing and optimizing test plans for silicon validation, driving the adoption of cutting-edge DFT tools and techniques, providing gui...

As a member of the Strategic Silicon Solutions (S3) Business Unit within AMD, your execution will help bring to life customers Special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more. We are seeking a highly experienced and motivated DFT (Design for Testability) Lead to join our dynamic team, with a strong background in implementing and managing DFT methodologies. The DFT Lead will be responsible for leading a team of engineers to develop and execute DFT strategies that ensure the highest level of product quality and reliability. Responsibilities Lead the design and implementation of advanced DFT architectures and methodol...

MTS SILICON DESIGN ENGINEER ? Job Title: Member of Technical Staff (MTS) SoC Scan and ATPG Experience: 6+ Location: Bangalore Job Description: We are looking for a talented Member of Technical Staff (MTS) with expertise in SoC Scan, Automatic Test Pattern Generation (ATPG), pattern retargeting, and simulations. The ideal candidate will play a crucial role in developing and verifying robust DFT solutions to ensure the quality and testability of our cutting-edge SoC designs. Key Responsibilities: Develop and execute SoC Scan insertion strategies and ensure integration across various modules. Generate and validate ATPG patterns to achieve high fault coverage for SoC designs. Perform pattern ret...

Sr DFT Engineers and Managers - location remote any where in India Job Summary Our clients Arasan Chip Systems (www.arasan.com) based in US are seeking for their India Development Center Senior and Experienced DFT Engineer with 68 years of hands-on expertise in Design-for-Test methodologies and implementation for complex SoC designs. The candidate will be responsible for developing and integrating DFT architectures, driving ATPG and MBIST flows, and working closely with RTL design, physical design, and test teams to ensure high test coverage and silicon readiness. Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan ...