Lead Physical Design Engineer Astera Labs

8.0 - 10.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com. Basic Qualifications Strong academic and technical background in electrical engineering. A Bachelor's de...

Posted 2 weeks ago

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PMTS Silicon Design Engineer Advanced Micro Devices, Inc

15.0 - 19.0 years

0 Lacs

karnataka

On-site

You will be part of the Strategic Silicon Solutions (S3) Business Unit at AMD, contributing to the realization of customers" special requirements for designs across a wide range of products. Your role as a DFT (Design for Testability) Lead involves implementing and managing DFT methodologies to ensure the quality and reliability of the products developed by the team. Your responsibilities will include leading the design and implementation of advanced DFT architectures and methodologies, collaborating with various teams to integrate DFT features seamlessly, developing and optimizing test plans for silicon validation, driving the adoption of cutting-edge DFT tools and techniques, providing gui...

Posted 1 month ago

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TS DFX Lead Advanced Micro Devices (AMD)

7.0 - 12.0 years

8 - 12 Lacs

Bengaluru, Karnataka, India

On-site

As a member of the Strategic Silicon Solutions (S3) Business Unit within AMD, your execution will help bring to life customers Special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more. We are seeking a highly experienced and motivated DFT (Design for Testability) Lead to join our dynamic team, with a strong background in implementing and managing DFT methodologies. The DFT Lead will be responsible for leading a team of engineers to develop and execute DFT strategies that ensure the highest level of product quality and reliability. Responsibilities Lead the design and implementation of advanced DFT architectures and methodol...

Posted 2 months ago

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MTS Silicon Design Engineer AMD

6.0 - 10.0 years

6 - 10 Lacs

Bengaluru, Karnataka, India

On-site

MTS SILICON DESIGN ENGINEER ? Job Title: Member of Technical Staff (MTS) SoC Scan and ATPG Experience: 6+ Location: Bangalore Job Description: We are looking for a talented Member of Technical Staff (MTS) with expertise in SoC Scan, Automatic Test Pattern Generation (ATPG), pattern retargeting, and simulations. The ideal candidate will play a crucial role in developing and verifying robust DFT solutions to ensure the quality and testability of our cutting-edge SoC designs. Key Responsibilities: Develop and execute SoC Scan insertion strategies and ensure integration across various modules. Generate and validate ATPG patterns to achieve high fault coverage for SoC designs. Perform pattern ret...

Posted 2 months ago

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Sr DFT Engineers & Managers - SOC Designs Assured Justice's Client

7.0 - 12.0 years

20 - 30 Lacs

Bengaluru

Remote

Sr DFT Engineers and Managers - location remote any where in India Job Summary Our clients Arasan Chip Systems (www.arasan.com) based in US are seeking for their India Development Center Senior and Experienced DFT Engineer with 68 years of hands-on expertise in Design-for-Test methodologies and implementation for complex SoC designs. The candidate will be responsible for developing and integrating DFT architectures, driving ATPG and MBIST flows, and working closely with RTL design, physical design, and test teams to ensure high test coverage and silicon readiness. Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan ...

Posted 3 months ago

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