LEAD SYSTEM ENGINEER PLATFORM & HARDWARE

• Deep expertise in eNB and gNB platform and hardware design, including bring-up initialization Sequence.
• Strong understanding of RU hardware design, eCPRI, PHY Split architectures (e.g., Split 7.2x), and SU/MU-MIMO systems.
• Hands-on experience with O-RAN Indoor Small Cell and Outdoor Micro Cell Hardware

• Architecture and Requirements, and exposure to O-RAN Network Energy Saving metrics and procedures.
• Proven experience with FSM10055 mmWave and FSM10056 Sub-6 GHz SoCs, including SDR RFIC and PHY integration.
• Design experience in SDR RFIC, DFE, and RFFE integration over COMe-based carrier boards.
• Familiarity with mezzanine based modular board system designs.ss
• Ability to deep dive ORAN HW reference designs.
• Ability to deep dive SoC (Qualcomm, Intel , EdgeQ) reference designs.
• Solid understanding of PMIC module for power profiling. Design knowledge of power reset circuits.
• Strong command over FPGA-based platforms and SoC integration, with practical use of MATLAB, VHDL for simulation and validation.
• Experience with Cadence Allegro for PCB schematic capture, layout review, and design verification.
• Skilled in resource profiling for system functions (e.g., baseband processing, RF chains, digital interfaces) and hardware controller/server board selection based on project-specific compute and IO demands.
• Ability to interface directly with ODM partners, articulate hardware requirements, define acceptance criteria, and ensure conformance to specifications.
• Knowledge of ATE-stage validation procedures, including calibration, PA/LNA linearization, and system-level MTBF and thermal analysis.
• Working knowledge of Dual Doherty PA.
• Hands-on involvement in SDR9000 RFIC, and validation of RFFE interfaces. Experience with QDART.
• Working knowledge hardware interfaces and IO expanders: SPI, UART, I2C.
• Proficiency in preparing Visio-based hardware block diagrams and managing hardware reference design documents.
• Ability to compile and manage Bill of Materials (BOM) accurately for system-level hardware builds.
• Familiarity with clock units, hard sync techniques, PTP, SyncE, and GPS modules for synchronization and timing architecture.
• Exposure to EDA tools (e.g., Synopsys, Cadence)
• Internship or thesis projects in semiconductor labs or companies
• Research publications in IEEE on digital/SoC/FPGA topics

• Master / PhD in Electronics and Communication Engineering, Digital Design, Embedded Systems Design or a related field.
• 15-20 years of experience in Wireless Embedded Platform Designs, with a strong foundation in LTE and 5G NR technologies with ORAN and 3GPP Knowledge.

Required Qualification: