Lead Software Engineer - DFT IP R&D

As a Lead Software Engineer - DFT IP R&D at Cadence Design Systems in Noida, you will be a crucial part of the R&D team working on the MODUS DFT software solution. MODUS is a comprehensive product aimed at achieving high coverage, reducing test time, and ensuring superior PPA. Your role will involve contributing to the development of innovative technologies in the DFT space, covering various aspects such as RTL design, DFT architecture, verification, power analysis, and optimization. **Key Responsibilities:** - Design and verify Verilog/SystemVerilog/UVM RTL and test benches for DFT IP features like full scan, memory BIST, JTAG, IEEE 1500, etc. - Provide R&D support for application and product engineers, including problem analysis and debugging for synthesis optimization. - Mentor and support team members to enhance their problem-solving skills and contribute effectively to the EDA problem domain. - Contribute to the development of cutting-edge design-for-testability tools, enhancing usability and quality through feature enrichment and rigorous verification. **Qualifications Required:** - Proficiency in RTL design using Verilog and SystemVerilog. - In-depth knowledge of front-end EDA tools like Verilog/SV simulators, CDC checkers. - Experience with SystemVerilog assertions, checkers, and advanced verification techniques. - Familiarity with scripting languages such as Perl or Python. - Strong foundational knowledge of data structures, algorithms, synthesis, and static timing analysis. - Excellent written and verbal communication skills. - Prior experience or understanding of EDA tool development concepts is advantageous. Cadence offers a challenging and innovative work environment where you will have the opportunity to work on impactful projects that push the boundaries of technology. Join us in solving problems that others can't, and be a part of a team dedicated to making a difference in the world of technology. As a Lead Software Engineer - DFT IP R&D at Cadence Design Systems in Noida, you will be a crucial part of the R&D team working on the MODUS DFT software solution. MODUS is a comprehensive product aimed at achieving high coverage, reducing test time, and ensuring superior PPA. Your role will involve contributing to the development of innovative technologies in the DFT space, covering various aspects such as RTL design, DFT architecture, verification, power analysis, and optimization. **Key Responsibilities:** - Design and verify Verilog/SystemVerilog/UVM RTL and test benches for DFT IP features like full scan, memory BIST, JTAG, IEEE 1500, etc. - Provide R&D support for application and product engineers, including problem analysis and debugging for synthesis optimization. - Mentor and support team members to enhance their problem-solving skills and contribute effectively to the EDA problem domain. - Contribute to the development of cutting-edge design-for-testability tools, enhancing usability and quality through feature enrichment and rigorous verification. **Qualifications Required:** - Proficiency in RTL design using Verilog and SystemVerilog. - In-depth knowledge of front-end EDA tools like Verilog/SV simulators, CDC checkers. - Experience with SystemVerilog assertions, checkers, and advanced verification techniques. - Familiarity with scripting languages such as Perl or Python. - Strong foundational knowledge of data structures, algorithms, synthesis, and static timing analysis. - Excellent written and verbal communication skills. - Prior experience or understanding of EDA tool development concepts is advantageous. Cadence offers a challenging and innovative work environment where you will have the opportunity to work on impactful projects that push the boundaries of technology. Join us in solving problems that others can't, and be a part of a team dedicated to making a difference in the world of technology.