Jobs

Interviews
Job Alerts
Tools

Upskill and Grow with AI

Mock Interview Practice interviews in realistic simulations

Coding Practice Improve your coding skills with challenges

Certification Earn certifications to validate your skills

AI Learning Get trained with AI expert sessions

Career Path AI insights for smarter career decisions

AI Job Match Score AI-Powered Job Match Against Your Resume and Optimize Your Resume

Career Tools and Resources

Resume Builder Build Professional Resume with Ease

ATS Friendliness Check Check Resume Friendliness for Applicant Tracking Systems

Auto Apply Apply to hundreds of jobs on any platform effortlessly

Co-Pilot (Chrome Extension) Your AI Assistant for Seamless Browsing Efficiency

Interview Questions Streamline interviews with ready-to-use questions

Salaries Discover market-driven salary insights across skillsets and geographies

Companies Explore leading companies actively hiring talent
For Employers

Jobs

Interviews

Home
>
Jobs in bengaluru
>
Mips
>
Lead DFT Engineer

Lead DFT Engineer

Mips

7 - 12 years

9 - 13 Lacs

bengaluru

Posted:1 day ago| Platform:

Apply

Skills Required

automation product engineering vhdl dft simulation analytical analog perl automotive python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Lead DFT Engineer

About MIPS

MIPS is a leader in high-performance RISC-V CPU IP, enabling innovation across automotive, AI, data center, and embedded markets. Our engineering teams are building the next generation of compute solutions, and we are looking for passionate talent to join us in shaping the future of semiconductors.

Position Overview

We are seeking an experienced Lead DFT Engineer to drive the architecture, implementation, and validation of Design for Test (DFT) solutions across complex SoCs. This role requires deep technical expertise in DFT flows, strong leadership skills, and proven ability to deliver high-quality, low-cost, and low-power test strategies for production silicon.

Key Responsibilities

Define and deploy DFT architecture for SoCs, including scan, ATPG, memory BIST, boundary scan, and analog test solutions.
Lead project-level DFT execution: schedule planning, task assignment, milestone tracking, and status reporting.
Drive pre-silicon verification of DFT IPs, including RTL generation, simulation, scan insertion, ATPG bring-up, and coverage analysis.
Collaborate with EDA vendors to optimize simulation and verification flows for DFT.
Partner with Test and Product Engineering teams for silicon bring-up, debug, and production test optimization.
Support STA constraints development and AMS verification for analog IP trims and characterization.
Mentor and ramp up junior engineers through training and technical guidance.
Contribute to automation, innovation, and continuous improvement of DFT methodologies.

Qualifications

M.Tech. in Microelectronics, Electronics or equivalent field (IISc or similar top-tier institute preferred).
B.Tech. in Electronics, Electrical Engineering.
7+ years of hands-on DFT experience, including SoC-level ownership.
Strong expertise in ATPG, scan insertion, memory BIST, STA, and analog, AMS test flows.
Proven track record of silicon bring-up and post-silicon debug.
Experience with DFT tools such as Cadence Genus, Modus, Xcelium, JasperGold, or similar.
Proficiency in SystemVerilog, VHDL and scripting languages (Python, Perl, Tcl, C).
Strong problem-solving skills, analytical mindset, and ability to lead cross-functional initiatives.

Preferred Skills

Prior experience driving low-power and cost-sensitive DFT architectures.
Contributions to patents, publications, or conference presentations in DFT, test.
Ability to work in a fast-paced environment with global teams.
Strong communication and leadership skills with a hands-on approach.

Why Join MIPS?

Be part of a team driving innovation in RISC-V CPU IP and SoC development.
Work on cutting-edge semiconductor designs with global impact.
Collaborative, growth-focused environment with opportunities for innovation and leadership.

More Jobs at Mips

Senior Technical Lead - Post-Silicon Validation & RTOS SDK

Pune, Bengaluru

10.0 - 15.0 yrs

INR 13 - 18 Lacs

Performance Benchmarking Lead

Bengaluru

10.0 - 15.0 yrs

INR 12 - 16 Lacs

Embedded Software Engineer - RTOS & Post-Silicon Validation

Pune

2.0 - 10.0 yrs

INR 5 - 9 Lacs

Design Verification Automation Engineer

Bengaluru

5.0 - 12.0 yrs

INR 7 - 11 Lacs

Senior Staff Engineer SOC DV

Bengaluru

8.0 - 10.0 yrs

INR 6 - 10 Lacs

Mock Interview

Practice Video Interview with JobPe AI

Start Python Interview

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.

Job Application AI Bot

Apply to 20+ Portals in one click

Download Now

Download the Mobile App

Instantly access job listings, apply easily, and track applications.

Enhance Your Python Skills

Practice Python coding challenges to boost your skills

Start Practicing Python Now

Mips

Login to

Please Verify Your Phone or Email

Confirm Action

Search

Profile

Upskill and Grow with AI

Lead DFT Engineer