Layout Design,Senior

You are a skilled Layout Engineer with 3-6 years of experience, specializing in Analog and Mixed-Signal IP layout. You have a background in Electronics or Electrical Engineering, holding a B.Tech or M.Tech degree. You possess a strong understanding of high-speed analog layout and have a solid grasp of CMOS and FinFET layouts. Your expertise extends to using CAD tools such as Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT. You are adapt at working independently, determining and developing solutions with minimal supervision. You frequently collaborate with senior personnel and are proactive in learning new technologies, demonstrating excellent analytical and problem-solving skills. Your strong communication skills enable effective interaction with internal development teams. What You'll Be Doing: Developing physical layout of high-speed Analog Integrated Circuits for the Analog and Mixed Signal IP group. Collaborating with a team of Analog/Mixed Signal Custom Layout Design Engineers on SerDes and Analog Mixed Signal IP blocks. Using advanced floor-planning techniques to optimize layout designs. Performing verification flows and ensuring compliance with DRC/LVS, LPE standards. Debugging and troubleshooting layout issues, utilizing your analytical skills. Providing regular updates to the manager on project status and networking with internal and external personnel. The Impact You Will Have: Contributing to the development of high-performance silicon chips that drive modern technology. Enhancing the reliability and efficiency of Analog and Mixed-Signal IP blocks. Ensuring the successful integration of high-speed signal layouts in cutting-edge applications. Improving the verification and validation processes through meticulous layout designs. Supporting the continuous innovation of Synopsys product offerings. Playing a key role in the development of next-generation electronic devices. What You'll Need: Experience in Analog Mixed-signal IP layout and verification of high-speed analog layout. Advanced understanding of Deep submicron effects and mitigation techniques. Expertise in CMOS and FinFET layouts and process technology. Familiarity with ESD and latchup layout design considerations. Proficiency in CAD tool usage, including Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT.