159 Innovus Jobs - Page 2

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

Job Description : KEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Ensuring timing correlation between PnR <-> STA and timely feedbacks to PD team Generating block level HS session and using Top context from SoC for Block-SoC Interface timing closure. Generating timing ECO using Tweaker/PrimeClosure. Job Requirement: PREFERRED EXPERIENCE: 5+ years of experience in timing closure of high frequency blocks (> GHz range) Analyzing the timing reports and identifying both design and constraints related issues. Worked on...

As a Physical Design Engineer based in Bangalore, India with over 3 years of experience, you will be responsible for various aspects of physical design for SoC using Innovus. Your key responsibilities will include floorplanning, IO ring creation, understanding ESD and latch-up requirements for foundry, and implementation strategies for placement. You will need to demonstrate expertise in hierarchical design implementation, including partitioning, push down methodologies, core/tile PG creation, and knowledge of analog components placement based on design specifications. Additionally, RDL knowledge and experience working with packaging are essential for SoC floorplan design. A critical aspect ...

Expertise in ASIC PD. Expertise in digital physical design Expertise in working with 3nm & 5nm technology nodes Expertise in EDA synthesis, APR, STA tools and methodologies Expertise in one or more of the following tools ICC, ICC2, Innovus , Olympus Working knowledge of one or more of the following tools Primetime, Calibre , and Red hawk Expertise in working with multi modes and multi corners STA Working Knowledge of multiple power planes and multiple VT libraries Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification Good at scripting languages PERL, TCL, shell Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes Debug,...

Physical design verification and Power analysis. Experienced with usage of tools Calibre, Innovus and Voltus Hands on layout edits in Innovus and analysis of power reports (IR, EM..etc) from Voltus Good experience in understanding DRC report from Calibre and fixing in Innovus, Good experience in understanding IR, EM reports from Voltus and fixing in Innovus. Working proficiency with tcl, AWK and python scripting. Previous experience with ADI flows preferred. Previous experience with power domain-based designs preferred

Experience : 4-10 Yrs Location : Blre 4-10 years experience with Bachelors degree in Electronics Engineering or equivalent Knowledgeable in all aspects of deep submicron ASIC design flow. Knowledgeable in Static Timing Analysis, Power Analysis and Innovus. Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages. Experience in developing PD metrics dashboard scripts for QOR tracking is a plus Experience in modifying STA constraints to check timing closure feasibility Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targe...

Wipro Limited is a leading technology services and consulting company dedicated to creating innovative solutions that cater to the most complex digital transformation requirements of clients. With a global presence spanning 65 countries and a workforce of over 230,000 employees and business partners, Wipro is committed to helping customers, colleagues, and communities thrive in an ever-evolving world. For more information, please visit www.wipro.com. As a Physical Design Lead, you will be based in Bangalore, Hyderabad, or Pune with a minimum of 8 years of experience. Your responsibilities will include handling Netlist2GDSII Implementation tasks such as Floor planning, Placement, CTS, Routing...

Who We Are Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world - like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. What We Offer Location: Bangalore,IND You'll benefit from...

Job Description Key Responsibilities: Timing Analysis & Closur e Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. Achieve timing closure by resolving violations and optimizing paths. Constraint Development Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths). Integrate constraints from multiple IPs for hierarchical STA. Tool Usage & Flow Integration Use STA tools like Synopsys PrimeTime, Cadence Tempus , or equivalent. Integrate STA into the overall design flow and automate processes for efficiency. Job Description: Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, an...

Job Description: Strong understanding of Physical Design with hands-on experience in RTL2GDS flow. Ability to close tiles/blocks including timing, noise, power, IR, phyV, conformal equivalence, and signoff checks. Exposure to advanced technology nodes (7nm and below) and related design challenges. Experience with the Synopsys tool suite is required. Knowledge of high-frequency design (>2GHz)

We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team. Key Responsibilities Work closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPs Carry out floor planning, and physically aware synthesis on high-performance IPs Perform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL team Leads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions...

4-10 years experience with Bachelors degree in Physical Design for Blre & Hyd Locations Good experience in ICC flow with Innovus tool Knowledgeable in Static Timing Analysis, Power Analysis and Innovus. Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages. Experience in developing PD metrics dashboard scripts for QOR tracking is a plus Experience in modifying STA constraints to check timing closure feasibility Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets Experience in FinFET & Dual Patterning nodes such a...

Responsibilities: Physical design verification and Power analysis. Experienced with usage of tools Calibre, Innovus and Voltus Hands on layout edits in Innovus and analysis of power reports from Voltus. Apply & share resume to mansoor@hisoltech.com

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electric...

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electric...

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications: Bachelors or Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering 5+ years of Hardware Engineering or related work expe...

Skills/Experience: Hands on debugging skills in different physical verification checks like LVS, DRC, ERC, PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. Working experience in cutting edge technologies such as 3/4/5nm and 7nm process nodes is desired Experience (years) : 4+ Year Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

Job Area: Engineering Group, Engineering Group Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance ...

Skills/Experience: Hands-on experience in complex SOC/sub-systems implementation using Innovus & Fusion Compiler. Proficient in top-down floorplan and Power Grid methodologies. Experience in signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff. Successful track records of taping out complex IPs & SoCs at 16/10/7/5 nm Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus . Automation and programming-minded, coding experience in Tcl/Tk/Perl. Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

As a Physical Design Engineer with 4+ years of experience, you will be responsible for Netlist2GDSII Implementation including Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, and Physical Verification. Your expertise should cover Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. Proficiency in programming languages like Tcl, Tk, and Perl is essential for this role. You should have hands-on experience with Synopsys and Cadence tools such as Innovus, ICC2, Primetime, PT-PX, and Calibre. Being well-versed in timing constraints, STA, and timing closure will be crucial for successful execution of projects. Your role will require ins...

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaborating with cross-functional teams, Qualcomm Hardware Engineers develop solutions that meet performance requirements. To qualify for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Enginee...

Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance die size optimization. What you will do: Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Work ...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Interfacing with customers regarding digital reference flows, including Synthesis Floorplanning Clock tree synthesis Power planning Place and route Timing closure Creating baseline flows to be used by customers as starting point for digital implementation Performing digital place and route and sign-off on small customer designs Creating documentation PPA optimization Bachelors degree with at least 4+ years of design/EDA experience or Masters degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digita...

Job Description We are seeking an experienced Digital Physical Design Lead to join our Motor drivers Digital design team. The ideal candidate will be responsible for leading physical design implementation of complex digital circuits from RTL to GDSII. Qualifications Key Responsibilities: Lead and mentor a team of physical design engineers Drive full chip physical implementation including synthesis, floor planning, power planning, placement, clock tree synthesis, and routing Develop and maintain physical design methodologies and flows Perform timing closure, power analysis, IR drop sign-off activities Interface with system architects, front-end design and verification teams to achieve optimum...