79 Innovus Jobs - Page 4

Directs and manages a team of PDK engineers focused on the quality assurance of process design kit (PDK) collateral for design (both internal and external) to enable new processes. Looking for candidate who is experienced in Custom Layout, SPICE Simulation, Physical Verification, APR expertise to drive end to end parasitic extraction tasks. Must have first-hand experience in working with industry standard EDA tools like Virtuoso, Spectre, Pegasus, Quantus RC, StarRC, ICV/IC Workbench, Fusion Compiler/ ICC2, Innovus, Calibre DRC/LVS/xact. Extraction space requires deep understanding of Technology changes at silicon level, able to interpret the FE,BE updates and drive the team to execute multiple QA checks and methodologies. Should be quick learner and help to the team to ungate the execution with thorough understanding of issues and quickly converge to solutions. Primary responsibility includes enablement of PDK Custom and ASIC extraction flows/ methodologies and test the PDK collaterals. Candidate is responsible in assuring the quality of Extraction decks by setting up various flows/methodologies driving the team members in developing required automation tasks. Should be self-driven and able to take up new tasks. Should closely interact with EDA vendors for enablement of new features / additions to the existing flows / methodologies. Provide support for internal customers, collaborate with EDA vendors for enhancement of the flows based on customer requests. Should be proficient in documenting the observations made from the flows executed. Automation of the key capabilities for design productivity is critical responsibility. Interfacing with PDK Dev teams, Cross Functional, EDA vendors, contracting employees. Oversees root cause analysis for issues related to designing to a specific process technology and drives initiatives and innovation to enhance design methodologies to develop high quality solutions and ensure ease of use for both internal and external design communities. Ensures all issues found during validation are filed in a ticketing database and ensure traction and closure before PDK release. Root causes QA misses and incoming customer issues and adds corrective actions to close gaps. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment. Qualifications Master's in EC or EE or CSE with 12+ yrs Exp or Bachelor's in EC or EE or CSE with 15+yrs industry experience in PDK development and QA. Experience in custom layout design methodology, ASIC physical design / PnR flow and industry standard tools for extraction (StarRC, QRC). Candidate should have good knowledge on semiconductor physics, process technology, EDA tools and associated challenges for advance technology. Candidate should be well versed with different parameters to optimize flow in terms of quality and resources. Must be proficient in automation using skill, tcl, python, perl and other scripting languages.Ability to be cognitively flexible and agile in a fast-changing software environment. Planning, prioritization, delegation skills are required. Excellent verbal and written communication is a must.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 10-15 years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Education Requirements Required:Bachelor's, Electrical Engineering or equivalent experiencePreferred:Master's, Electrical Engineering or equivalent experience Keywords Innovus, FC, UPF, STA, Formal Verification, Genus, Primetime, Tempus, SOD Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

• 5+ years of EXP. in Analog Layout • Hands-On with CAD tools like Cadence Virtuoso XL, PVS/Calibre or Synopsys IC Validator, StarRC • Proficient at debugging/fixing LVS/DRC errors • EXP. with synthesis/advanced P&R (Innovus) is a plus Required Candidate profile • Work with circuit designers to complete the Physical Layout & Verification of High-Performance, Low-Power AMS CMOS IC's. • Solid understanding of semiconductor manufacturing process & DFM techniques

As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- 1) Place and Route, CTS, Routablity analysis with respect to congestion. 2) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) 3) Integration of analog blocks, Meeting RC requirements for manual/special signals 4) Good understanding of calibre rule deck of DRC/LVS/DFM,DFY, ERC and ESD latchup. 5) Responsible for all the integrity checks (chip finishing) and post Tapeout eJob view release, 6) Good scripting knowledge perl and TCL, familiar with caliber, Innovus, 7) Understanding of VLSI fabrication process, 8) Implementing timing ECOs. Implementing IR drop fixes, SPEF extraction, signal EM fixes, Noise analysis. 9) Open to new responsibilities in context of rapid technological change. 10) Good communication skills, work closely with the team members to accomplish PD milestone. 11) Secondary competencies :- Good understanding of CTS, STA, PTSI and timing. Relevant experience of CAD tools cadence Innovus, Calibre is preferred. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.