Job
Description
Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for an experience Verification Staff/Architect Engineer, who will be responsible Verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.) which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle. Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure Debug of regression signatures and identifying bug fixes Responsible for Quality sign off and required documentation Developing/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) Debug and root cause post silicon issues in collaboration with Design, SW and test teams Work with SoC level performance modeling team on latency, bandwidth analysis " Required skillset include Strong debugging, Analytical and problem-solving skills Expertise on UVM based verification Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Communication and collaboration skills to work with a large world-wide design organization " Desired skillset includes Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Qualification : Bachelor/Masters Degree in Electronics & Communication / Micro Electronics 9 -12 years of experience Experience with UVM and ARM Bus protocols. tor, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
