403 Floor Planning Jobs - Page 6

Key Responsibilities: Portfolio & Recovery Management: Manage and monitor recovery efforts on NPA (Non-Performing Assets), write-off, and hard bucket accounts (e.g., 180+ DPD). Develop account-wise recovery strategies, including field follow-ups, settlements, and legal recourse. Track daily, weekly, and monthly performance of recovery pools; ensure achievement of recovery targets. Agency & Vendor Management: Empanel, onboard, and supervise third-party collection agencies and recovery agents. Monitor agency performance through scorecards, audits, and field visits. Train and guide agency teams to adhere to bank standards and recovery protocols. Legal Coordination: Liaise with the legal team for SARFAESI actions, Lok Adalat, arbitration, Section 138 (cheque bounce), civil suits, and other recovery tools. Ensure timely filing and tracking of legal cases for recovery. Maintain documentation and MIS related to legal proceedings and settlements. Compliance & Governance: Ensure adherence to regulatory guidelines (e.g., RBI) and internal audit standards for recovery processes. Handle customer escalations and ensure a professional and ethical approach to recoveries. Submit timely reports, MIS, and updates to senior management. Location - M umbai,Delhi / NCR ,Pune,Bangalore,Hyderabad,Chennai

About The Role Skill required: Network Services - Cisco Routing and Switching Operations Designation: Business Advisory Associate Qualifications: Any Graduation Years of Experience: 1 to 3 years About Accenture Combining unmatched experience and specialized skills across more than 40 industries, we offer Strategy and Consulting, Technology and Operations services, and Accenture Song all powered by the worlds largest network of Advanced Technology and Intelligent Operations centers. Our 699,000 people deliver on the promise of technology and human ingenuity every day, serving clients in more than 120 countries. Visit us at www.accenture.com What would you do "Helps transform back office and network operations, reduce time to market and grow revenue, by improving customer experience and capex efficiency, and reducing cost-to-serveLooking for a candidate who has expertise in Networking and has good knowledge on fundamentals of NetworkA solution that validates the ability to install, configure, operate, and troubleshoot medium-size route and switched networks." What are we looking for "Agility for quick learningAbility to work well in a teamProcess-orientationWritten and verbal communicationNetwork fundamentalsUnderstanding all the networking devices:Routers, switches, etc.IP connectivity, access, addressing, and servicesNetwork security fundamentalsInstallation, Configuration, Operation, Administration, and Troubleshooting Fundamental IPv4 & IPv6 Business NetworksExcellent CommunicationProblem Solving SkillsFlexibilityTeamworkExperience and working knowledge on OSI Layer 1 (Physical) and 2 (Datalink) troubleshooting (WAN point to point connection) Experience and working knowledge with IP, WAN, OSI layer, TCP/IP models, IPv4/v6 addressing, subnetting and Ethernet. Layer 1 to Layer 3 fault isolation and troubleshooting with telco providers and onsite technicians. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Familiarity with SDH, SONET, and Ethernet concepts Basic knowledge of cabling infrastructure such as patch panels, cross-connects and fiber types. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Experience working with global carriers in North America, LATAM, APAC, and/or EMEA Experience working in a multi-vendor DWDM optical environment Good English written/verbal communication and customer engagement skills Strong focus on providing an outstanding user experience Must be detail-oriented, with strong organizational skills Able to work independently and also in a team environment" Roles and Responsibilities: "In this role you are required to solve routine problems, largely through precedent and referral to general guidelines Your expected interactions are within your own team and direct supervisor You will be provided detailed to moderate level of instruction on daily work tasks and detailed instruction on new assignments The decisions that you make would impact your own work You will be an individual contributor as a part of a team, with a predetermined, focused scope of work Please note that this role may require you to work in rotational shiftsProvide 24/7/365 monitoring of ticket queue, phones, and IRC channelManage network events such as:Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updatesLink Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - FamiliarityProvide 24/7/365 monitoring of ticket queue, phones, and IRC channelManage network events such as:Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updatesLink Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity and understanding of router show commands and how to interpret the outputManage client s optical network, manage alarms and faults in a multi-vendor environment, andTracking of all work in ticketing system network interconnects with internal and external network operatorsTrack and maintain a repository of RFOs and vendor improvements/actions and be able to represent client during external calls with 3rd party providersManage troubleshooting, confirming fix and restoring traffic from network incidents reported by internal teams and third-party teams, engaging field resources and inventory teams as necessary.Track, coordinate and manage hardware recalls / minor card or part replacement, RMA part delivery, initiate production change requests and work with onsite techs for faulty card/part replacementRead/Parse vendor notifications and translate to Clients Production Change Request (PCR s)Look up affected circuits to include them in change requestEscalate any emergency change requests for immediate review and schedulingNavigate ambiguity with unclear notifications from vendors - escalating as necessary or referring notification to other internal client teams" Qualification Any Graduation

About The Role Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : SAP FI S/4HANA Accounting Good to have skills : NAMinimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Developer, you will be involved in designing, building, and configuring applications to meet business process and application requirements. Your typical day will revolve around creating innovative solutions to address specific business needs and ensuring seamless application functionality. Roles & Responsibilities:- Liaising with clients to gather necessary requirements and resolve GST-related queries.- Configuring and maintaining GST settings in SAP, including TDS, E-invoice, and other tax-related modules.- Configuring and Testing of GST returns (Document compliance Reporting), To ensure compliance with GST laws and regulations.- Proficient in implementing and handeling third party integration- Join Cluster Tax team, focusing on localization and deployment- he/she will need to have experience in/with SAP tax reporting or tax determination- he/she will support tax localization requirements during the full project lifecycle.- he/she will review build demos and test results against design/- he/she will support country users in organizational change activities and ensure country users know & act on their responsibilities- he/she will perform cutover and hypercare activities- Expected to be an SME- Collaborate and manage the team to perform- Responsible for team decisions- Engage with multiple teams and contribute on key decisions- Provide solutions to problems for their immediate team and across multiple teams- Lead the team in implementing best practices for SAP FI S/4HANA Accounting- Conduct regular code reviews and ensure adherence to coding standards- Stay updated with the latest trends in SAP FI S/4HANA Accounting and provide training to team members Professional & Technical Skills: - Strong knowledge of GST laws and regulations.- Proficiency in SAP FICO with experience in end-to-end implementations.- SAP Experience in baseline configuration for GST India in SAP. Experience in SAP FI, MM, and SD.- Must To Have Skills: Proficiency in SAP FI S/4HANA Accounting- Strong understanding of financial accounting principles- Experience in configuring and customizing SAP FI modules- Knowledge of integration with other SAP modules- Hands-on experience in SAP implementation projects- SAP Tax Accounting- SAP S/4HANA Finance- SAP Tax reporting- SAP Tax determination- SAP ARC/DRC is a plus Additional Information:- The candidate should have a minimum of 7.5 years of experience in SAP FI S/4HANA Accounting- This position is based at our Hyderabad office- A 15 years full-time education is required Qualification 15 years full time education

Positions are open for full-time and co-op/internship in the areas of CPU and SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power. Responsibilities Own block level design from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff. Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure. Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA. Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV. Requirements Knowledge using synthesis, place & route, analysis and verification CAD tools. Familiarity with logic & physical design principles to drive low-power & higher-performance designs. Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL. Good understanding of device physics and experience in deep sub-micron technologiesKnowledge of Verilog and SystemVerilog. Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated. Ability to work well in a team and be productive under aggressive schedules. Education and Experience PhD, Master s Degree or Bachelor s Degree in technical subject area.

Physical Design (4-10 years experience) Please share details to abarna.e@hcltech.com Company: HCL Tech Job Summary: We are looking for a highly motivated and experienced Physical Design Lead to join our dynamic team and play a vital role in the physical design and implementation of next-generation integrated circuits (ICs). This leadership role offers the opportunity to leverage your expertise in physical design methodologies and lead a team in achieving successful tapeouts. Responsibilities: Leadership: Lead and manage a team of physical design engineers, fostering a collaborative and high-performing work environment Delegate tasks, provide technical guidance, and mentor junior engineers to ensure their professional development Motivate and inspire the team to achieve project goals and deadlines Foster a culture of continuous learning and knowledge sharing within the physical design group Physical Design Expertise: Define and implement the overall physical design strategy for assigned projects, considering factors like performance, power, and area Perform floorplanning, placement, clock tree synthesis (CTS), and routing for complex digital circuits Ensure adherence to design rules and manufacturability guidelines Utilize physical design tools and methodologies (place and route tools, static timing analysis tools) to achieve timing closure and optimal physical design Collaborate with design, verification, and layout teams to ensure seamless integration throughout the design flow Participate in design reviews and provide technical leadership on physical design aspects Project Management: Manage physical design project schedules and budgets, ensuring timely completion within resource constraints Track project progress, identify potential risks, and implement mitigation strategies Communicate project status and challenges effectively to stakeholders (engineering leadership, product management) Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 4-10 years of solid experience in physical design of ASICs or SoCs Proven track record of leading and mentoring a physical design team to successful tapeouts In-depth knowledge of physical design methodologies (floorplanning, placement, routing, CTS, static timing analysis) Expertise in industry-standard physical design tools (place and route tools, static timing analysis tools) Strong understanding of digital design concepts and principles (combinational logic, sequential logic) Excellent problem-solving and analytical skills with a focus on achieving timing closure and design optimization Effective communication, collaboration, and leadership skills to motivate and guide the team Ability to manage multiple projects, prioritize tasks, and meet deadlines Benefits: Competitive salary and benefits package commensurate with experience Opportunity to lead a team and influence the physical design of cutting-edge technologies Collaborative and dynamic work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions

AMRITSAR GROUP OF COLLEGES is looking for Assistant Placement Officer to join our dynamic team and embark on a rewarding career journey Career Counseling: Provide guidance and career counseling to students or job seekers, helping them identify their skills, interests, and career goals Job Placement: Facilitate job placements by matching candidates with suitable job openings based on their qualifications and preferences Employer Engagement: Build and maintain relationships with employers, businesses, and organizations to understand their hiring needs and requirements Job Postings and Recruitment: Post job vacancies and coordinate recruitment processes, including conducting interviews and coordinating selection procedures Resume and Interview Preparation: Assist candidates in preparing resumes, cover letters, and interview techniques to enhance their chances of securing a job Internship and Training Opportunities: Identify and promote internship and training opportunities for students and job seekers to gain practical experience Networking Events: Organize job fairs, networking events, and industry-specific workshops to connect candidates with potential employers

Role & responsibilities A VLSI (Very Large Scale Integration) Recruiter typically focuses on finding and hiring talent with expertise in semiconductor design, integrated circuit (IC) design, and VLSI technologies. Below are some of the key roles and responsibilities for a VLSI Recruiter position: 1. Talent Acquisition Sourcing Candidates: Actively source candidates for VLSI design roles, including hardware engineers, design engineers, verification engineers, and other related positions within the semiconductor industry. Job Postings: Create detailed job descriptions, post open positions on job boards, and engage with potential candidates through professional networks like LinkedIn. Screening Resumes: Review resumes and applications to identify qualified candidates based on skills and experience relevant to VLSI design roles. Interviewing Candidates: Conduct initial screening interviews to evaluate candidates' technical skills, experience, and cultural fit. Coordinate Interviews: Schedule interviews with hiring managers, VLSI engineers, and technical teams, ensuring a smooth interview process. 2. Collaboration with Hiring Managers Understand Requirements: Work closely with hiring managers and team leads to understand the specific needs for VLSI roles and the required skill set for each position. Technical Knowledge: Gain a solid understanding of the technical requirements for VLSI design and verification positions to effectively screen candidates. 3. Candidate Relationship Management Build a Talent Pool: Maintain a network of passive candidates for future opportunities, especially for hard-to-fill roles or specialized positions. Candidate Engagement: Keep candidates engaged throughout the hiring process, providing them with feedback, updates, and insights into the company culture and the role. Negotiations: Negotiate offers with candidates, ensuring alignment on salary, benefits, and other terms of employment. If interested, Please share me your updated resume to rama.c@acesoftlabs.com Regards, Rama CH Key Account Manager (KAM) Acesoft Labs

Physical Design (4-10 years experience) Share your details to @abarna.e@gmail.com Company: HCL Tech Job Summary: We are looking for a highly motivated and experienced Physical Design Lead to join our dynamic team and play a vital role in the physical design and implementation of next-generation integrated circuits (ICs). This leadership role offers the opportunity to leverage your expertise in physical design methodologies and lead a team in achieving successful tapeouts. Responsibilities: Leadership: Lead and manage a team of physical design engineers, fostering a collaborative and high-performing work environment Delegate tasks, provide technical guidance, and mentor junior engineers to ensure their professional development Motivate and inspire the team to achieve project goals and deadlines Foster a culture of continuous learning and knowledge sharing within the physical design group Physical Design Expertise: Define and implement the overall physical design strategy for assigned projects, considering factors like performance, power, and area Perform floorplanning, placement, clock tree synthesis (CTS), and routing for complex digital circuits Ensure adherence to design rules and manufacturability guidelines Utilize physical design tools and methodologies (place and route tools, static timing analysis tools) to achieve timing closure and optimal physical design Collaborate with design, verification, and layout teams to ensure seamless integration throughout the design flow Participate in design reviews and provide technical leadership on physical design aspects Project Management: Manage physical design project schedules and budgets, ensuring timely completion within resource constraints Track project progress, identify potential risks, and implement mitigation strategies Communicate project status and challenges effectively to stakeholders (engineering leadership, product management) Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in physical design of ASICs or SoCs Proven track record of leading and mentoring a physical design team to successful tapeouts In-depth knowledge of physical design methodologies (floorplanning, placement, routing, CTS, static timing analysis) Expertise in industry-standard physical design tools (place and route tools, static timing analysis tools) Strong understanding of digital design concepts and principles (combinational logic, sequential logic) Excellent problem-solving and analytical skills with a focus on achieving timing closure and design optimization Effective communication, collaboration, and leadership skills to motivate and guide the team Ability to manage multiple projects, prioritize tasks, and meet deadlines Benefits: Competitive salary and benefits package commensurate with experience Opportunity to lead a team and influence the physical design of cutting-edge technologies Collaborative and dynamic work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions

Role & responsibilities 1. Creates 2D CAD Technical drawings and floor plans 2. Develop concepts, mood boards, and space plans tailored to the brief 3. Create 2D drawings and 3D renders using design software (e.g., AutoCAD, SketchUp, Revit) 4. Help to select furniture, materials, finishes, lighting, and dcor elements 5. Coordinate with Sales team member, Client and Project Manager to understand Requirement 6. Creates Mood Boards, representing the theme 7. Finishing a design in 2 days 8. Visits vendors & market with client for selection 9. Does rendering for designs made by Design Managers 10. Make site visits for understanding the space and proper dimensions Preferred candidate profile 1. Degree in Interior Design or a related field 2. Proficiency in design tools such as AutoCAD, SketchUp, Photoshop, Revit, or similar 3. Strong understanding of materials, color theory, and spatial planning 4. Excellent communication and presentation skills 5. Ability to multitask and meet deadlines in a fast-paced environment 6. Passion for design and a keen eye for detail

Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 5 years of experience with physical design. Experience with Python or C++. Experience with machine learning. Preferred qualifications: 10 years of experience in synthesis and physical design. Experience in various machine learning algorithms from logistic regression to neural networks and reinforcement learning. Understanding of algorithms and data structures. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Machine Learning Engineer for the Google silicon organization, you will contribute to improving SoC Performance, Power, and Area (PPA) using machine learning techniques. You will apply your experience to solve technical issues and drive improvements in Power, Performance, Area, and Schedule. You will directly impact logic design and optimization, floorplanning, place and route, clock and power planning, timing analysis, Power Delivery Network (PDN) analysis, and more. You will collaborate across Alphabet, working with design, CAD, and machine learning teams. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Deploy Google s AI solutions into chip design, collaborating with internal teams, Google DeepMind, and other teams within Google to explore and apply solutions that improve chip design PPA or reduce cycle time.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the job In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes.

Responsibilities - Work with the business and IT team to identify, analyze, and translate business requirements into comprehensive design documents (RDD, FDD, TDD etc.,) - Thorough understanding of Floorplan & Factoring flow and Financial products in the Wholesale Financing products. - Hands on experience on .NET X, HTML, .Net Core, WEB AP. - Lead and be part of strategy in ERP system implementations, upgrades, and support with strong focus on ensuring that Finance, Treasury and Accounting Data is following policies as well as securitization servicing and reporting requirements - Thorough understanding in requirement analysis and technical evaluation, with a strong command of cloud technologies such as Azure, AWS etc., and implement solutions with frameworks such as JavaScript (React, Angular) and .NET, MVC, React, Redux, React Hooks, Typescript, Web Pack, Full Story, Material UI, JS, HTML5, Web Sockets. - Lead technology modernization efforts and perform regular scan and resolution of critical security vulnerabilities to keep applications on modern frameworks with zero technical debt. - Lead in developing Apps and Portals using Microsoft Stack like PowerApps, Power BI and Share point Online. - Lead identification of process breakdowns, controllership issues in IT systems and implementation of automations to improve - Design, implement, and support automated, reliable, and available IT solutions - Lead testing efforts including documenting Test Scenarios & Test Cases - Work with Developers to ensure projects are on track and meet expectations - Configure ERP Financial modules, lead SIT/Regression testing with end-to-end scenarios and coordinate with onsite and offshore teams. Prepare training materials and perform training for end users - Utilize Six Sigma / Lean and Agile Project Management tools to track and maintain projects progress - Lead project teams to ensure milestones are met. Provide updates to IT and Business Leadership - Assist with management of key vendor reviews at the time of contract renewal or when lack of quality and/or service warrant review. Minimum Requirements : - Bachelors degree - At least 8 years of experience analyzing, designing, evaluating, modifying, testing and implementing enterprise-wide systems or business experience using ERP applications - At least 5 years of strong Technical/Functional experience in systems or modules of Floorplan & Factoring, Document Management, API Integration Engines. - Leading skills in Development, deployment of API technologies such as SOAP, REST, JSON, XML, gRPC, GraphQL etc., - Proven success with design, testing, and training on new implementations/ enhancements of Wholesale Financing projects. Shift Timing : 2 :30pm until 12 :00am IST

Associate -Store Planner Back to job search results Tesco India Bengaluru, Karnataka, India Hybrid Full-Time Permanent Apply by 11-Jul-2025 About the role Refer to Responsibilities What is in it for you At Tesco, we are committed to providing the best for you. As a result, our colleagues enjoy a unique, differentiated, market- competitive reward package, based on the current industry practices, for all the work they put into serving our customers, communities and planet a little better every day. Our Tesco Rewards framework consists of pillars - Fixed Pay, Incentives, and Benefits. Total Rewards offered at Tesco is determined by four principles - simple, fair, competitive, and sustainable. Salary - Your fixed pay is the guaranteed pay as per your contract of employment. Performance Bonus - Opportunity to earn additional compensation bonus based on performance, paid annually Leave & Time-off - Colleagues are entitled to 30 days of leave (18 days of Earned Leave, 12 days of Casual/Sick Leave) and 10 national and festival holidays, as per the company s policy. Making Retirement Tension-FreeSalary - In addition to Statutory retirement beneets, Tesco enables colleagues to participate in voluntary programmes like NPS and VPF. Health is Wealth - Tesco promotes programmes that support a culture of health and wellness including insurance for colleagues and their family. Our medical insurance provides coverage for dependents including parents or in-laws. Mental Wellbeing - We offer mental health support through self-help tools, community groups, ally networks, face-to-face counselling, and more for both colleagues and dependents. Financial Wellbeing - Through our financial literacy partner, we offer one-to-one financial coaching at discounted rates, as well as salary advances on earned wages upon request. Save As You Earn (SAYE) - Our SAYE programme allows colleagues to transition from being employees to Tesco shareholders through a structured 3-year savings plan. Physical Wellbeing - Our green campus promotes physical wellbeing with facilities that include a cricket pitch, football field, badminton and volleyball courts, along with indoor games, encouraging a healthier lifestyle. You will be responsible for Job Summary: Ensure delivery of high quality plans within defined targets and as per defined ways of working for Range changes and Development stores In this job, I am accountable for: - Following our Business Code of Conduct and always acting with integrity and due diligence - Identifying operational improvements and finding solutions by applying CI tools and techniques - Responsible for completing tasks and transactions within agreed metrics - Knows and applies fundamental work theories/concepts/processes in own areas of work - Planning micro or macro layouts and adjacencies for stores in line with agreed principles and strategies - Using Space and Floor Planning tools to build and maintain high quality plans for stores - Keeping self up to date with process changes - Following the defined Quality Assurance Processes and framework Key people and teams I work People, budgets and other resources with in and outside of Tesco: I am accountable for in my job: Space, Range and Merchandising - BLR & Markets NA Onestop - Markets Customer and Product Teams - BLR & Markets People Operations - BLR Property - BLR & Markets Operational skills relevant for this job: Experience relevant for this job: Basic Auto CAD, Relevant domain experience in Store Planning JDA Floor Planning or any space planning platform knowledge, Intermediate Space planning concepts Basic MS Office ( Excel, Word, PPT) You will need Refer to Responsibilities About us Tesco in Bengaluru is a multi-disciplinary team serving our customers, communities, and planet a little better every day across markets. Our goal is to create a sustainable competitive advantage for Tesco by standardising processes, delivering cost savings, enabling agility through technological solutions, and empowering our colleagues to do even more for our customers. With cross-functional expertise, a wide network of teams, and strong governance, we reduce complexity, thereby offering high-quality services for our customers. Tesco in Bengaluru, established in 2004 to enable standardisation and build centralised capabilities and competencies, makes the experience better for our millions of customers worldwide and simpler for over 3,30,000 colleagues. Tesco Business Solutions: Established in 2017, Tesco Business Solutions (TBS) has evolved from a single entity traditional shared services in Bengaluru, India (from 2004) to a global, purpose-driven solutions-focused organisation. TBS is committed to driving scale at speed and delivering value to the Tesco Group through the power of decision science. With over 4,400 highly skilled colleagues globally, TBS supports markets and business units across four locations in the UK, India, Hungary, and the Republic of Ireland. The organisation underpins everything that the Tesco Group does, bringing innovation, a solutions mindset, and agility to its operations and support functions, building winning partnerships across the business. TBSs focus is on adding value and creating impactful outcomes that shape the future of the business. TBS creates a sustainable competitive advantage for the Tesco Group by becoming the partner of choice for talent, transformation, and value creation Apply

Responsibilities - Work with the business and IT team to identify, analyze, and translate business requirements into comprehensive design documents (RDD, FDD, TDD etc.,) - Thorough understanding of Floorplan & Factoring flow and Financial products in the Wholesale Financing products. - Hands on experience on .NET X, HTML, .Net Core, WEB AP. - Lead and be part of strategy in ERP system implementations, upgrades, and support with strong focus on ensuring that Finance, Treasury and Accounting Data is following policies as well as securitization servicing and reporting requirements - Thorough understanding in requirement analysis and technical evaluation, with a strong command of cloud technologies such as Azure, AWS etc., and implement solutions with frameworks such as JavaScript (React, Angular) and .NET, MVC, React, Redux, React Hooks, Typescript, Web Pack, Full Story, Material UI, JS, HTML5, Web Sockets. - Lead technology modernization efforts and perform regular scan and resolution of critical security vulnerabilities to keep applications on modern frameworks with zero technical debt. - Lead in developing Apps and Portals using Microsoft Stack like PowerApps, Power BI and Share point Online. - Lead identification of process breakdowns, controllership issues in IT systems and implementation of automations to improve - Design, implement, and support automated, reliable, and available IT solutions - Lead testing efforts including documenting Test Scenarios & Test Cases - Work with Developers to ensure projects are on track and meet expectations - Configure ERP Financial modules, lead SIT/Regression testing with end-to-end scenarios and coordinate with onsite and offshore teams. Prepare training materials and perform training for end users - Utilize Six Sigma / Lean and Agile Project Management tools to track and maintain projects progress - Lead project teams to ensure milestones are met. Provide updates to IT and Business Leadership - Assist with management of key vendor reviews at the time of contract renewal or when lack of quality and/or service warrant review. Minimum Requirements : - Bachelors degree - At least 8 years of experience analyzing, designing, evaluating, modifying, testing and implementing enterprise-wide systems or business experience using ERP applications - At least 5 years of strong Technical/Functional experience in systems or modules of Floorplan & Factoring, Document Management, API Integration Engines. - Leading skills in Development, deployment of API technologies such as SOAP, REST, JSON, XML, gRPC, GraphQL etc., - Proven success with design, testing, and training on new implementations/ enhancements of Wholesale Financing projects. Shift Timing : 2 :30pm until 12 :00am IST

Your Role and Responsibilities 1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

Job Title: AI/ML Engineer - Time Series Forecasting & Clustering Location: Bangalore Experience: 2+ Years Job Type: Full-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting : Build models to predict trends from time series data. Clustering : Develop algorithms to group and analyze data segments. Data Insights : Analyze data to enhance model performance. Team Collaboration : Work with teams to integrate models into products. Stay Updated : Apply the latest AI techniques to improve solutions. Qualifications: Education : Bachelors/Masters in Computer Science or related field. Experience : Hands-on experience with time series forecasting and clustering. Skills : Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and Wellness: Healthcare policy covering your family and parents. Food: Enjoy scrumptious buffet lunch at the office every day. Professional Development: Learn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and Recognitions: Recognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto? Health & Family: Comprehensive benefits for you and your loved ones, ensuring well-being. Growth Mindset: Continuous learning opportunities to stay ahead in your field. Dynamic & Inclusive: Vibrant culture fostering collaboration, creativity, and belonging. Career Ladder: Internal promotions and clear path for advancement. Recognition & Rewards: Celebrate your achievements and contributions. Work-Life Harmony: Flexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: Bachelor’s or Master’s degree from a top-tier institute. 5+ years of experience in STA/Timing from product-based companies. Job : STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience 7 to 15 years Physical design of block level with full understanding of PnR cycle. Good understanding of Physical design fundamentals Good hands-on experience on industry standard pnr tools like ICC2/Innovus Good understanding on signoff tool like Prime time , Redhawk and calibre Should be able to guide junior engineers in resolving technical issues. Tools ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS ScriptingTCL, Perl

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 2+ years Hardware Engineering experience or related work experience. 2+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 3+ years Hardware Engineering experience or related work experience. 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelors or master’s in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools – Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages – , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational RequiredBachelor's, Electrical Engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 8+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Additional General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 5+ years Hardware Engineering experience or related work experience. 5+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 5+ years Hardware Engineering experience or related work experience. 5+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 8+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm