Senior Analog and Digital Mask Design Engineer

Role Overview: As a Senior Analog and Digital Mask Design Engineer at NVIDIA, you will be part of a dynamic team responsible for handling challenging analog circuit designs. Your primary focus will be executing IC layout of cutting-edge, high-performance CMOS integrated circuits in various foundry process nodes. You will play a key role in driving the identification and resolution of complex physical design issues, mentoring junior engineers, and ensuring design quality by adhering to industry best practices. Key Responsibilities: - Execute IC layout of high-performance CMOS integrated circuits in foundry process nodes ranging from 2nm to 7nm and lower, following industry best practices. - Optimize all physical verification activities, including DRC, LVS, density analysis, and tape-out checks. - Develop analog layouts, lead solving efforts, and drive optimization for performance, area, and manufacturability. - Cultivate effective teamwork across multi-functional teams, influence project direction, and ensure alignment with organizational objectives. - Lead and perform full custom layout of analog/mixed-signal blocks such as op-amps, bandgaps, PLLs, ADCs, DACs, LDOs, Voltage Regulators, etc. - Represent the team in technical discussions with customers, excel in resource management, and mentor junior engineers in established methodologies. Qualifications Required: - 8+ years of experience in high-performance analog layout in advanced CMOS process. - BE/M-Tech in Electrical & Electronics or equivalent experience. - Thorough knowledge of industry-standard EDA tools, specifically for Cadence. - Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps, etc. - Knowledge of analog design and layout guidelines, high-speed IO, and other analog-specific guidelines. - Experience with floor planning, block-level routing, and macro-level assembly. - Demonstrated experience with analog layout for silicon chips in mass production. - Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred. - Experience working in distributed design teams is a plus.,