403 Floor Planning Jobs - Page 5

Skills requried: • In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes. - Should have experience in Analog and Mixed Signal Design • Should have experience in handling >5M instance count , 1.5GHz frequency designs . • Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency. • Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2) • Strong experience on Static Timing Analysis (PrimeTime - SI) , EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). • Understanding the practical application of methodologies and Physical Design Tools, Flow Automation, and Improvements. • Experience in complex SOC integration, Low Power and High-Speed Design and Advanced Physical Verification Techniques.

As an IC Layout Manager at Micron Technology, you will have the opportunity to work with a talented core team based in India, focusing on designing IC layouts for applications such as artificial intelligence and high-performance computing solutions, including High Bandwidth Memory. Your role will involve collaborating with global teams to ensure the successful completion of multiple projects within scheduled milestones. Your responsibilities will include: - Building and growing a Custom layout team to support Micron's global DRAM layout requirements. - Developing Analog and custom layout designs to meet project schedules and milestones. - Training team members in technical skills and fostering a healthy team culture. - Communicating effectively with engineering teams across different regions to ensure project success. - Organizing, prioritizing, and managing tasks and resources for multiple projects. - Performance management and development of team members. - Leading hiring and retention efforts. - Contributing to the overall success of Micron's DRAM India operation. To qualify for this role, you should have: - 14+ years of experience in analog/custom layout in advanced CMOS processes. - Minimum 1+ year of people management experience. - Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS. - Strong skills in layout, floor planning, and manual routing. - Ability to build and develop a premier analog/mixed-signal layout team. - Experience in managing multiple Custom IC layout projects. - Motivation, attention to detail, and a systematic approach in IC layout design. - Excellent communication skills and the ability to work effectively in a team and fast-paced environment. - Strong analytical skills, creative thinking, and self-motivation. - Capability to work in a cross-functional, multi-site team environment. - Previous experience in DRAM/NAND layout design is desirable. - Passion for attracting, hiring, and retaining engineers with an innovative mindset. - Collaboration skills with overseas teams to define and execute strategies across the organization. - Accountability for the technical solutions implemented by your team. Education requirements for this role include a BE or MTech in Electronic/VLSI Engineering. Micron Technology, Inc. is a global leader in innovative memory and storage solutions, dedicated to transforming information usage for the betterment of all. Through a focus on technology leadership and operational excellence, Micron delivers high-performance memory and storage products that drive advancements in artificial intelligence and 5G applications. For more information about Micron Technology, Inc., please visit micron.com/careers. If you require assistance with the application process or need reasonable accommodations, please contact hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and adheres to all relevant labor laws, regulations, and international standards.,

AMRITSAR GROUP OF COLLEGES is looking for Assistant Placement Officer to join our dynamic team and embark on a rewarding career journey. Career Counseling : Provide guidance and career counseling to students or job seekers, helping them identify their skills, interests, and career goals. Job Placement : Facilitate job placements by matching candidates with suitable job openings based on their qualifications and preferences. Employer Engagement : Build and maintain relationships with employers, businesses, and organizations to understand their hiring needs and requirements. Job Postings and Recruitment : Post job vacancies and coordinate recruitment processes, including conducting interviews and coordinating selection procedures. Resume and Interview Preparation : Assist candidates in preparing resumes, cover letters, and interview techniques to enhance their chances of securing a job. Internship and Training Opportunities : Identify and promote internship and training opportunities for students and job seekers to gain practical experience. Networking Events : Organize job fairs, networking events, and industry - specific workshops to connect candidates with potential employers.

PHYSICAL DESIGN ENGINEER (4 6 YEARS) - Incise & CMI (Cornell Medical Instruments) PHYSICAL DESIGN ENGINEER (4 6 YEARS) 2025-04-18T06:11:54+00:00 Skills : Calibre,ICC2,Perl,TCL Job Locations : Hyderabad Total vacancies : 3 Experience on EMIR analysis for multiple modes, including; static and dynamic with/without functional vectors Should have expertise in understanding and debugging EMIR issues in a block level. Power analysis for the blocks. Experience on Floor-planning, Place & route, power and clock distribution, pin placement. In-depth knowledge on industry leading tools like Redhawk, Olympus/ICC2, Primetime, and Calibre Knowledge of package modeling, package and chip level analysis is added advantage Good understanding of Physical design verification using Calibre. Knowledge of Synthesis and DFT is added advantage. Prior experience with 16nm or finer geometries is a plus. Proficient use of tcl/Perl Must have good communication skills and self-driven individual. To apply for . Our team will contact you for further details. Job Category: PHYSICAL DESIGN ENGINEER Job Type: Full Time Job Location: Hyderabad Apply for this position Allowed Type(s): .pdf, .doc, .docx By using this form you agree with the storage and handling of your data by this website. *

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT.: Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI HVL Verification. Experience: 3-5 Years.

The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT. Experience: 3-5 Years.

Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipros Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc Mandatory Skills: VLSI Physical Design Planning. Experience: 8-10 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route Experience: 3-5 Years

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI HVL Verification Experience: 3-5 Years

The position will involve working with a very experienced physical design team and is responsible for delivering the physical design of blocks/tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation chips in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 5-7 years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Requirements 1. Lead High Performance ARM Core Hardening Job Title: Lead Engineer ARM Core Hardening Location: BLR/Hyd Experience: 812 years Technology Node: 5nm/3nm/2nm FinFET/GAA Reports To: Director/Technical Manager SoC Implementation Key Responsibilities: Lead end-to-end RTL-to-GDSII hardening of ARM Cortex-A/X/Neoverse cores (single and multi-cluster). Collaborate with RTL, CAD, DFT, low power, and architecture teams to define floorplan and implementation strategy. Own full flow: floorplanning, power planning (UPF-based), placement, CTS, routing, ECO, timing closure, physical verification, and signoff. Drive design quality metrics: PPA (Performance, Power, Area), DRC/LVS clean, IR drop, EM, and thermal-aware optimization. Architect physical implementation methodology tailored to ARM hardening: hierarchical flow, black-boxing strategy, physical partitioning, clocking architecture. Interface with foundry and EDA vendors for process tech enablement and tool issues. Technical Skills: Deep understanding of ARM core microarchitecture (pipeline, fetch/decode, FPU/NEON, L1/L2 cache). Expert in Synopsys/Cadence tools: ICC2/Fusion Compiler, Tempus/Innovus, Primetime, StarRC, RedHawk/Totem. Advanced clock tree design: CCOpt, custom H-trees, mesh, and multi-source CTS. Experience with UPF-based low power flows and Conformal Low Power (CLP) verification. Familiarity with physical-aware DFT and scan compression (test-mode aware synthesis/placement). Familiar with physical architecture trade-offs (voltage islands, power domains, channel management). Knowledge of EMIR, thermal, aging-aware closure in HPC-class cores. Experience taping out at 5nm or lower is mandatory. --- 2. Engineer ARM Core Hardening Job Title: Physical Design Engineer ARM Core Hardening Location: BLR/Hyd Experience: 38 years Technology Node: 5nm/3nm/2nm FinFET/GAA Key Responsibilities: Implement physical design of ARM core and subsystems from RTL to GDSII. Responsible for floorplanning, placement, CTS, routing, timing and physical closure of core logic. Perform static timing analysis, IR/EM validation, and physical verification. Optimize for frequency, leakage, and area within power and thermal budgets. Support integration of hardened cores into SoC top-level environment. Technical Skills: Good understanding of ARM core architecture and pipeline structure. Experience in Synopsys or Cadence PnR and signoff tools (ICC2, Fusion Compiler, Innovus, PT, RedHawk). Experience in UPF flows, CPF/UPF constraints, and low-power verification tools. Good in timing ECOs, DFT integration, scan reordering and hold fixing in low power designs. Strong debugging skills: congestion, IR drop, setup/hold, crosstalk, antenna, and DRC. Familiar with scripting (TCL, Python, Perl) to automate flows and reports. Work Experience Lead High Performance ARM Core Hardening Experience working with ARM POP (Processor Optimization Pack) or ARM Artisan Physical IP. Worked with multi-core cluster hardening and coherent interconnects (e. g. , CMN-600). Experience with RTL-based performance modeling and correlation with implementation ARM Core Engineer: ARM POP usage experience. Previous tapeout at \u22647nm. Exposure to hierarchical and multi-voltage designs. Familiarity with advanced floorplanning constraints for multi-core clusters.

Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization. Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems. Drive automation and validation of timing and physical design data across subsystem boundaries. Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams. Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration. Exhibit excellent communication skills to present technical solutions and lead discussions with internal teams and customers, especially regarding subsystem-level trade-offs and integration Qualifications 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below). Demonstrated expertise in STA tools (e. g. , Synopsys PrimeTime, Cadence Tempus) and PNR tools (e. g. , Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems. Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems. Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks. Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems. Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred. Background high-speed interfaces, or mixed-signal SoC subsystems

The role requires a Physical Design Engineer with a strong foundation in the basic fundamentals of C-MOS technology. You are expected to possess a deep understanding of the PD Flow for both flat and hierarchal designs. Your responsibilities will include independently handling RTL/Netlist to GDSII at block level/SS/SoC and having experience in multiple tape outs with a focus on low power implementation. Experience in floor planning, Partitioning, integration at Subsystem/Chip will be considered an advantage. You should have practical experience with Lower technology nodes such as 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, and 28nm. Proficiency in floor planning, placement optimizations, CTS, and routing is essential. You must have hands-on experience in block/top level signoff STA, physical verification checks (DRC/LVS/ERC/antenna), and other reliability checks (IR/EM/Xtalk). Familiarity with industry standard EDA tools from Synopsys, Cadence, and Mentor such as ICC2, Fusion-Compiler, Design Compiler, Primetime, PTSI, IC Validator, Innovus, Genus, Tempus, Encounter, Nanoroute, Calibre, StarRC, Redhawk, and voltage storm is required. Exposure to DMSA flow for ECO generation and implementation is beneficial. A good understanding of VLSI process and proficiency in scripting using TCL, Perl are necessary. Key Skills: Physical design, Innovus, Floor Planning, Signoff STA,

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Mandatory Skills: VLSI Physical Verification. Experience: 5-8 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Design Planning. Experience: 1-3 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI HVL Verification. Experience: 3-5 Years.

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degreein Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Mandatory Skills: VLSI Physical Verification. Experience: 5-8 Years.

Manage all student progress and prepare required strategies to overcome issues. Arranging for guest lectures. Arranging visits to the local parlors for the students. Arranging Induction & different sessions too. Looking after placements for students of hub center Maintaining pre placement and post-placement data and sharing it with the central office. Checking the quality of training at the centers and submitting reports about the same. Taking an initiative in creating new placement partnerships and tie ups in coordination with the Central team. Track the students for the complete period of their employment in the city. Provide mentor-ship support to students employed in the region to help them settle down including counseling, helping with finding accommodation, resolving issues with employers, helping establish social network in city, providing any other emergency support in the city Capture feedback of students and recruiters on an ongoing basis. Build and maintain regular connections with current and past employers & clients. Requirements Willingness to travel regularly Minimum Qualification Graduation 1 years of experience in the field Own two wheeler with required documents Basic Computer knowledge (Microsoft Excel & Word, Internet, etc.) Good Communications Skills Fluency in English, Hindi & the Regional Language (Kannad) Experience/ interest in training, teaching & coordinating.

Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipros Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc Mandatory Skills: VLSI Physical Design Planning.Experience8-10 Years.

Responsibilities - Work with the business and IT team to identify, analyze, and translate business requirements into comprehensive design documents (RDD, FDD, TDD etc.,) - Thorough understanding of Floorplan & Factoring flow and Financial products in the Wholesale Financing products. - Hands on experience on .NET X, HTML, .Net Core, WEB AP. - Lead and be part of strategy in ERP system implementations, upgrades, and support with strong focus on ensuring that Finance, Treasury and Accounting Data is following policies as well as securitization servicing and reporting requirements - Thorough understanding in requirement analysis and technical evaluation, with a strong command of cloud technologies such as Azure, AWS etc., and implement solutions with frameworks such as JavaScript (React, Angular) and .NET, MVC, React, Redux, React Hooks, Typescript, Web Pack, Full Story, Material UI, JS, HTML5, Web Sockets. - Lead technology modernization efforts and perform regular scan and resolution of critical security vulnerabilities to keep applications on modern frameworks with zero technical debt. - Lead in developing Apps and Portals using Microsoft Stack like PowerApps, Power BI and Share point Online. - Lead identification of process breakdowns, controllership issues in IT systems and implementation of automations to improve - Design, implement, and support automated, reliable, and available IT solutions - Lead testing efforts including documenting Test Scenarios & Test Cases - Work with Developers to ensure projects are on track and meet expectations - Configure ERP Financial modules, lead SIT/Regression testing with end-to-end scenarios and coordinate with onsite and offshore teams. Prepare training materials and perform training for end users - Utilize Six Sigma / Lean and Agile Project Management tools to track and maintain projects progress - Lead project teams to ensure milestones are met. Provide updates to IT and Business Leadership - Assist with management of key vendor reviews at the time of contract renewal or when lack of quality and/or service warrant review. Minimum Requirements : - Bachelors degree - At least 8 years of experience analyzing, designing, evaluating, modifying, testing and implementing enterprise-wide systems or business experience using ERP applications - At least 5 years of strong Technical/Functional experience in systems or modules of Floorplan & Factoring, Document Management, API Integration Engines. - Leading skills in Development, deployment of API technologies such as SOAP, REST, JSON, XML, gRPC, GraphQL etc., - Proven success with design, testing, and training on new implementations/ enhancements of Wholesale Financing projects. Shift Timing : 2 :30pm until 12 :00am IST

Responsibilities - Work with the business and IT team to identify, analyze, and translate business requirements into comprehensive design documents (RDD, FDD, TDD etc.,) - Thorough understanding of Floorplan & Factoring flow and Financial products in the Wholesale Financing products. - Hands on experience on .NET X, HTML, .Net Core, WEB AP. - Lead and be part of strategy in ERP system implementations, upgrades, and support with strong focus on ensuring that Finance, Treasury and Accounting Data is following policies as well as securitization servicing and reporting requirements - Thorough understanding in requirement analysis and technical evaluation, with a strong command of cloud technologies such as Azure, AWS etc., and implement solutions with frameworks such as JavaScript (React, Angular) and .NET, MVC, React, Redux, React Hooks, Typescript, Web Pack, Full Story, Material UI, JS, HTML5, Web Sockets. - Lead technology modernization efforts and perform regular scan and resolution of critical security vulnerabilities to keep applications on modern frameworks with zero technical debt. - Lead in developing Apps and Portals using Microsoft Stack like PowerApps, Power BI and Share point Online. - Lead identification of process breakdowns, controllership issues in IT systems and implementation of automations to improve - Design, implement, and support automated, reliable, and available IT solutions - Lead testing efforts including documenting Test Scenarios & Test Cases - Work with Developers to ensure projects are on track and meet expectations - Configure ERP Financial modules, lead SIT/Regression testing with end-to-end scenarios and coordinate with onsite and offshore teams. Prepare training materials and perform training for end users - Utilize Six Sigma Lean and Agile Project Management tools to track and maintain projects progress - Lead project teams to ensure milestones are met. Provide updates to IT and Business Leadership - Assist with management of key vendor reviews at the time of contract renewal or when lack of quality and/or service warrant review. Minimum Requirements : - Bachelors degree - At least 8 years of experience analyzing, designing, evaluating, modifying, testing and implementing enterprise-wide systems or business experience using ERP applications - At least 5 years of strong Technical/Functional experience in systems or modules of Floorplan & Factoring, Document Management, API Integration Engines. - Leading skills in Development, deployment of API technologies such as SOAP, REST, JSON, XML, gRPC, GraphQL etc., - Proven success with design, testing, and training on new implementations/ enhancements of Wholesale Financing projects. Shift Timing : 2 :30pm until 12 :00am IST

Job Overview: We are looking for a highly motivated and detail-oriented Block-Level Physical Design Engineer (4+ Years) to join our dynamic VLSI team. You will be responsible for driving the complete physical implementation of complex digital blocks using industry-standard tools and methodologies, targeting advanced technology nodes including 2 nm/3nm and beyond. Key Responsibilities: Execute block-level physical design activities including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing , and Physical Verification . Perform Static Timing Analysis (STA) , IR drop analysis, RC extraction , and ensure power, timing, and signal integrity closure. Work hands-on with tools like Cadence Innovus , Synopsys ICC2 , Primetime , RedHawk , etc. Handle congestion analysis , design optimization , and area/power/timing trade-offs to meet PPA targets. Collaborate with RTL design, DFT, and verification teams to ensure seamless integration and clean handoff. Contribute to timing closure , ECO implementation, and physical sign-off.

As a Principal Physical Design Engineer focusing on New Product Development in Power Management at OnSemi in Bengaluru, India, you will play a crucial role in the development of Power management products for various applications such as consumer, industrial, and automotive sectors. Your responsibilities will include leading the P&R process, power planning, floor planning, clock tree building, congestion analysis for complex multi-power domain designs, and continuously seeking improvements in existing flows and methods to enhance Performance, Power, and Area (PPA) metrics. Your role will require strong problem-solving skills with a deep understanding of technical issues, allowing you to collaborate effectively with both analog and digital technical staff members. You should possess a comprehensive understanding of the end-to-end digital design flow and have hands-on experience in IR & power analysis tools and flows. Proficiency in Verilog, TCL, and Perl/Python programming languages is essential for this position. Onsemi, a company focused on driving disruptive innovations in automotive and industrial end-markets, aims to create intelligent power and sensing technologies to address complex global challenges. The company's innovative product portfolio contributes to building a safer, cleaner, and smarter world by leveraging megatrends like vehicle electrification, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. To qualify for this role, you should hold a Bachelor's degree in Electrical Engineering or a related field with at least 8 years of experience, or a Master's degree with 7 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. Your expertise should cover RTL design, ASIC synthesis, timing analysis, CDC, P&R, and UPF methodologies. Additionally, a proven track record of releasing complex ICs to the market and excellent cross-functional communication skills are required to succeed in this position. At Onsemi, we are dedicated to attracting high-performance innovators and providing a positive recruitment experience for all candidates, reflecting our commitment to being a great place to work. If you are passionate about driving innovation in Power Management and contributing to a better future, we encourage you to join our dynamic team and be part of our journey towards creating a more sustainable and intelligent world.,