988 Floor Planning Jobs - Page 31

Physical Deisgn Lea LocationBangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experienceon Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes....

Job Description. Arm’s CE-Systems DFT team implements DFT for test chips and hard macros to prove out Arm soft IP power, performance, area, and functionality within the context of an SoC using the latest DFT and process technologies. The DFT team works closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.. Responsibilities. Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate a...

To work as a Frontend engineer and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects.. Job Description. In your new role you will:. Implement high-performance, low-power, and area-efficient digital designs.. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis.. Optimize designs for power, performance, and area, and meet PPA goals.. Power analysis using PT-PX or equivalent flow.. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs.. Define and evaluate constraints and signoff Test/DFT mode timing requirements.. Your Profile. You are best equipped for this task if you have:. Strong fund...

Physical Design Full Chip Low Power verification 10+ yrs

We are looking for Physical Design Engineers with Exp in Low Power Verification with above 10yrs Exp

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL de...

Physical Design Implementation: Experience in block and SoC level PD implementation, covering the entire flow from netlist to GDSII, including PnR/APR. Low Power Design: Proficient in low power design techniques. Flow Expertise: Hands-on experience with floorplanning, power planning, placement, CTS (Clock Tree Synthesis), routing, extraction, and DFM (Design for Analysis Skills: Strong ability to perform congestion and timing analysis, with a focus on achieving better QoR (Quality of Results). Sign-Off Expertise: In-depth knowledge of sign-off processes including STA (Static Timing Analysis), DRC/LVS/Antenna/ERC checks, power analysis, IR/EM analysis, LEC (Logic Equivalence Checking), and EC...

Urgent hiring for Junior Architect / Interior designer Office Layout & Design Location: Gurugram Department: Projects / Design Compensation: Based on experience Role Overview: We are looking to hire a Junior Architect /Draftsman with a strong background in preparing CAD layouts and experience in office interior design. The selected candidate will be part of the design team by producing detailed interior drawings and assisting with spatial planning for managed and flexible office spaces. Key Responsibilities: Develop and modify 2D CAD layouts for office interiors, including furniture layouts, electrical layouts, and partition plans Assist in space planning and optimizing floor plans as per cl...

Blue Yonder's Space & Floor Planning Consultant Configure and implement space/floor planning tools. Analyze retail data for planogram optimization. Provide technical support and documentation.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Requirements: Strong layout knowledge with a minimum of 3 to 4 years of experience Applicants must hold a Bachelors degree Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools. Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc Experienced in digital (standard cell, memory, I/O) layout Experienced in analog layout is also a plus Job Description: Responsible to understand and apply...

Roles and Responsibilities Good experience in PD execution of multiple medium to High critical blocks/HMs from Netlist to GDSII Develop and qualify the methodology and implementation flow in advanced technologies like 14nm and below. Well versed with FC/Innovus tools and good understanding of place/cts/Route critical settings Develop expertise in ASIC Synthesis, Floor Planning, STA (Static Timing Analysis), and other relevant technologies. Good experience in Low power designs Conduct thorough analysis of designs to identify potential issues and implement solutions. Perform physical design activities including floor planning, PNR (Physical Netlist) creation, and timing closure using Innovus t...

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration amo...

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times I...

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime. This role is based in Ban...

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in ...

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise a...

Roles and Responsibilities Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis, Place and Route, STA, timing and physical signoffs Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/F...

Supervise and support sales staff, providing training and development as needed. Ensure excellent customer service standards are met consistently. Manage daily operations including opening and closing procedures. Oversee store presentation and merchandise displays. Maintain accurate inventory records and perform regular stock audits. Address customer inquiries and resolve any issues promptly. Collaborate with the sales team to achieve sales targets and KPIs. Ensure compliance with company policies and procedures.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Requirements: Strong layout knowledge with a minimum of 6 to 10 years of experience Applicants must hold a Bachelors degree Skills include Cadence layout, Cadence schematic capture, using CALIBRE Hercules verification tools. Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc Experienced in digital (standard cell, memory, I/O) layout Experienced in analog layout is also a plus Job Description: Responsible to understand and apply ...

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Requirements: Strong layout knowledge with a minimum of 3 to 4 years of experience Applicants must hold a Bachelors degree Skills include Cadence layout, Cadence schematic capture, using CALIBRE Hercules verification tools. Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc Experienced in digital (standard cell, memory, I/O) layout Experienced in analog layout is also a plus Job Description: Responsible to understand and apply a...

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Requirements: Strong layout knowledge with a minimum of 6 to 10 years of experience Applicants must hold a Bachelors degree Skills include Cadence layout, Cadence schematic capture, using CALIBRE Hercules verification tools. Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc Experienced in digital (standard cell, memory, I/O) layout Experienced in analog layout is also a plus Job Description: Responsible to understand and apply ...

Job Details: : You will be part of ACE India , in the P- Core design team driving Intels latest CPUs in the latest process technology. In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in PNR from RTL to GDSII. Your responsibilities will include but not limited to:Meet the design targets of high performance and low-power digital design.Static timing analysis.Power Optimization.Design Convergence Experience at IP, SoC level.Ability to work in a highly dynamic environment across geographies.Back end design and implementation of new features.7Post silicon performance push activities. Qualifications: You must possess a Masters Degree in Electrical or...

Job Details: : Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU micro...

Proficient in AutoCAD and AutoTrack Background in Civil Engineering/Drafting,Available for site visits if required (within Kolkata)

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implement...